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a ADUC812 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective companies. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?2003 analog devices, inc. all rights reserved. rev. d microconverter , multichannel 12-bit adc with embedded flash mcu functional block diagram microcontroller 8051 based microcontroller core power supply monitor watchdog timer 640 8 user flash eeprom 256 8 user ram spi 12-bit successive approximation adc adc control and calibration logic t/h temp sensor 2.5v ref ain mux buf dac0 mosi/ sdata miso (p 3.3) sclock txd (p 3.1) rxd (p 3.0) xtal2 xtal1 dgnd dv dd agnd av dd dac0 dac1 t0 (p3.4) t1 (p3.5) t2 (p1.0) t2ex (p1.1) int0 (p3.2) int1 (p3.3) ale psen ea reset ADUC812 p3.0?3.7 p2.0?2.7 p1.0?1.7 p0.0?0.7 ain0 (p1.0)?in7 (p1.7) v ref uart 8k 8 program flash eeprom dac control 3 16-bit timer/counters osc mux dac1 buf c ref buf 2-wire serial i/o features analog i/o 8-channel, high accuracy 12-bit adc on-chip, 100 ppm/ c voltage reference high speed 200 ksps dma controller for high speed adc-to-ram capture 2 12-bit voltage output dacs on-chip temperature sensor function memory 8k bytes on-chip flash/ee program memory 640 bytes on-chip flash/ee data memory 256 bytes on-chip data ram 16m bytes external data address space 64k bytes external program address space 8051 compatible core 12 mhz nominal operation (16 mhz max) 3 16-bit timer/counters high current drive capability?ort 3 9 interrupt sources, 2 priority levels power specified for 3 v and 5 v operation normal, idle, and power-down modes on-chip peripherals uart and spi serial i/o 2-wire (400 khz i 2 c compatible) serial i/o watchdog timer power supply monitor applications intelligent sensors calibration and conditioning battery-powered systems (portable pcs, instruments, monitors) transient capture systems das and communications systems con tro l loop monitors (optical networks/base stations) general description the ADUC812 is a fully integrated 12-bit data acquisition system incorporating a high performance self-calibrating multichannel adc, dual dac, and programmable 8-bit mcu (8051 instruc- tion set compatible) on a single chip. the programmable 8051 compatible core is supported by 8k bytes flash/ee program memory, 640 bytes flash/ee data memory, and 256 bytes data sram on-chip. additional mcu support functions include watchdog timer, power supply monitor, and adc dma functions. thirty-two pro grammable i/o lines, i 2 c compatible spi and standard uart serial port i/o are provided for multiprocessor inter faces and i/o expansion. normal, idle, and power-down operating modes for both the m cu core and analog converters allow flexible power manage- ment schemes suited to low power applications. the part is specified for 3 v and 5 v operation over the industrial tem- perature range and is available in a 52-lead, plastic quad flatpack package, and in a 56-lead, chip scale package.
rev. d ADUC812 ? features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 applicatons . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . 6 pin configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 pin function descriptions . . . . . . . . . . . . . . . . . . . . . 7 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 adc specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 integral nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 differential nonlinearity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 offset error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 full-scale error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 signal to (noise + distortion) ratio . . . . . . . . . . . . . . . . . . . . 8 total harmonic distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 dac specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 relative accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 voltage output settling time . . . . . . . . . . . . . . . . . . . . . . . . . 8 digital-to-analog glitch impulse . . . . . . . . . . . . . . . . . . . . . . . 8 architecture, main features . . . . . . . . . . . . . . . . . . 9 memory organization . . . . . . . . . . . . . . . . . . . . . . . . . . 9 overview of mcu-related sfrs . . . . . . . . . . . . . . . . . 10 accumulator sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 b sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 stack pointer sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 data pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 program status word sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 power control sfr . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 special function registers . . . . . . . . . . . . . . . . . . . 11 adc circuit information . . . . . . . . . . . . . . . . . . . . . . 12 general overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 adc transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 typical operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 adccon1?adc control sfr #1) . . . . . . . . . . . . . . . . . 13 adccon2?adc control sfr #2) . . . . . . . . . . . . . . . . . 14 adccon3?adc control sfr #3) . . . . . . . . . . . . . . . . . 14 driving the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 voltage reference connections . . . . . . . . . . . . . . . . . . . . . . . 16 configuring the adc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 adc dma mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 dma mode configuration example . . . . . . . . . . . . . . . . . . . 17 micro operation during adc dma mode . . . . . . . . . . . . . . 17 offset and gain calibration coefficients . . . . . . . . . . . . . . . . 17 calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 nonvolatile flash memory . . . . . . . . . . . . . . . . . . . 18 flash memory overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 flash/ee memory and the ADUC812 . . . . . . . . . . . . . . . . . . 18 ADUC812 flash/ee memory reliability . . . . . . . . . . . . . . . . 18 using the flash/ee program memory . . . . . . . . . . . . . . . . . . 19 using the flash/ee data memory . . . . . . . . . . . . . . . . . . . . . 19 econ?lash/ee memory control sfr . . . . . . . . . . . . . . . 20 flash/ee memory timing . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 using the flash/ee memory interface . . . . . . . . . . . . . . . . . . 20 erase-all . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 program a byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 user interface to other on-chip ADUC812 peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 using the dac . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 power supply monitor . . . . . . . . . . . . . . . . . . . . . . . . . 24 serial peripheral interface . . . . . . . . . . . . . . . . . . . 25 miso (master in, slave out data i/o pin) . . . . . . . . . . . . . . 25 mosi (master out, slave in pin) . . . . . . . . . . . . . . . . . . . . . 26 sclock (serial clock i/o pin) . . . . . . . . . . . . . . . . . . . . . . 26 ss (slave select input pin) . . . . . . . . . . . . . . . . . . . . . . . . . . 26 using the spi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 spi interface?aster mode . . . . . . . . . . . . . . . . . . . . . . . . . 27 spi interface?lave mode . . . . . . . . . . . . . . . . . . . . . . . . . . 27 i 2 c compatible interface . . . . . . . . . . . . . . . . . . . . . . 28 8051 compatible on-chip peripherals . . . . . . . . . . 29 parallel i/o ports 0? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 timers/counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 timer/counters 0 and 1 data registers . . . . . . . . . . . . . . . . . 31 th0 and tl0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 th1 and tl1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 timer/counters 0 and 1 operating modes . . . . . 32 mode 0 (13-bit timer/counter) . . . . . . . . . . . . . . . . . . . . . . 32 mode 1 (16-bit timer/counter) . . . . . . . . . . . . . . . . . . . . . . 32 mode 2 (8-bit timer/counter with auto reload) . . . . . . . . . 32 mode 3 (two 8-bit timer/counters) . . . . . . . . . . . . . . . . . . 32 timer/counter 2 data registers . . . . . . . . . . . . . . . . . . . . . . 33 th2 and tl2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 rcap2h and rcap2l . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 timer/counter operation modes . . . . . . . . . . . . . . . . . . . . . 34 16-bit autoreload mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 16-bit capture mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 uart serial interface . . . . . . . . . . . . . . . . . . . . . . . . . 35 mode 0 (8-bit shift register mode) . . . . . . . . . . . . . . . . . . . 36 mode 1 (8-bit uart, variable baud rate) . . . . . . . . . . . . . . 36 mode 2 (9-bit uart with fixed baud rate) . . . . . . . . . . . . 36 mode 3 (9-bit uart with variable baud rate) . . . . . . . . . . 36 uart serial port baud rate generation . . . . . . . . . . . . . . . 36 timer 1 generated baud rates . . . . . . . . . . . . . . . . . . . . . . . 37 timer 2 generated baud rates . . . . . . . . . . . . . . . . . . . . . . . 37 interrupt system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 interrupt priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 ADUC812 hardware design considerations . . . . 40 clock oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 external memory interface . . . . . . . . . . . . . . . . . . . . . . . . . . 40 power-on reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . 41 power supplies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 power consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 grounding and board layout recommendations . . . . . . . . . 43 other hardware considerations . . . . . . . . . . . . . 44 in-circuit serial download access . . . . . . . . . . . . . . . . . . . . 44 embedded serial port debugger . . . . . . . . . . . . . . . . . . . . . . 44 single-pin emulation mode . . . . . . . . . . . . . . . . . . . . . . . . . . 45 enhanced-hooks emulation mode . . . . . . . . . . . . . . . . . . . . 45 typical system configuration . . . . . . . . . . . . . . . . . . . . . . . . 45 quickstart development system . . . . . . . . . . . . . 45 download?n-circuit serial downloader . . . . . . . . . . . . . . . 45 debug?n-circuit debugger . . . . . . . . . . . . . . . . . . . . . . . . 45 adsim?indows simulator . . . . . . . . . . . . . . . . . . . . . . . . 45 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . 46 outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 table of contents
rev. d ? ADUC812 specifications 1, 2 (av dd = dv dd = 3.0 v or 5.0 v 10%, ref in /ref out = 2.5 v internal reference, mclkin = 11.0592 mhz, f sample = 200 khz, dac v out load to agnd; r l = 2 k , c l = 100 pf. all specifications t a = t min to t max , unless otherwise noted.) ADUC812bs parameter v dd = 5 v v dd = 3 v unit test conditions/comments adc channel specifications dc accuracy 3, 4 resolution 12 12 bits integral nonlinearity 1/2 1/2 lsb typ f sample = 100 khz 1.5 1.5 lsb max f sample = 100 khz 1.5 1.5 lsb typ f sample = 200 khz differential nonlinearity 1 1lsb typ f sample = 100 khz. guaranteed no missing codes at 5 v calibrated endpoint errors 5, 6 offset error 5 5lsb max 1 1lsb typ offset error match 1 1 lsb typ gain error 6 6lsb max 1 1lsb typ gain error match 1.5 1.5 lsb typ user system calibration 7 offset calibration range 5 5 % of v ref typ gain calibration range 2.5 2.5 % of v ref typ dynamic performance f in = 10 khz sine wave f sample = 100 khz signal-to-noise ratio (snr) 8 70 70 db typ total harmonic distortion (thd) ?8 ?8 db typ peak harmonic or spurious noise ?8 ?8 db typ analog input input voltage ranges 0 to v ref 0 to v ref v leakage current 1 1 m a max 0.1 0.1 m a typ input capacitance 9 20 20 pf max temperature sensor 10 voltage output at 25 c 600 600 mv typ can vary significantly (> 20%) voltage tc ?.0 ?.0 mv/ c typ from device to device dac channel specifications dc accuracy 11 resolution 12 12 bits relative accuracy 3 3lsb typ differential nonlinearity 0.5 1l sb typ guaranteed 12-bit monotonic offset error 60 60 mv max 15 15 mv typ full-scale error 30 30 mv max 10 10 mv typ full-scale mismatch 0.5 0.5 % typ % of full-scale on dac1 analog outputs voltage range_0 0 to v ref 0 to v ref v typ voltage range_1 0 to v dd 0 to v dd v typ resistive load 10 10 k w typ capacitive load 100 100 pf typ output impedance 0.5 0.5 w typ i sink 50 50 m a typ
rev. d ? ADUC812 specifications 1, 2 (continued) ADUC812bs parameter v dd = 5 v v dd = 3 v unit test conditions/comments dac ac characteristics voltage output settling time 15 15 m s typ full-scale settling time to within 1/2 lsb of final value digital-to-analog glitch energy 10 10 nv sec typ 1 lsb change at major carry reference input/output ref in input voltage range 9 2.3/v dd 2.3/v dd v min/max input impedance 150 150 k w typ ref out output voltage 2.5 2.5% 2.5 2.5% v min/max initial tolerance @ 25 c 2.5 2.5 v typ ref out tempco 100 100 ppm/ c typ flash/ee memory performance characteristics 12, 13 endurance 10,000 cycles min 50,000 50,000 cycles typ data retention 10 years min watchdog timer characteristics oscillator frequency 64 64 khz typ power supply monitor characteristics power supply trip point accuracy 2.5 2. 5% of selected nominal trip point voltage max 1.0 1. 0% of selected nominal trip point voltage typ digital inputs input high voltage (v inh ) 2.4 2.4 v min xtal1 input high voltage (v inh ) only 4 v min input low voltage (v inl ) 0.8 0.8 v max input leakage current (port 0, ea) 10 10 m a max v in = 0 v or v dd 1 1 m a typ v in = 0 v or v dd logic 1 input current (all digital inputs) 10 10 m a max v in = v dd 1 1 m a typ v in = v dd logic 0 input current (port 1, 2, 3) ?0 ?0 m a max ?0 ?0 m a typ v il = 450 mv logic 1-0 transition current (port 1, 2, 3) ?00 ?00 m a max v il = 2 v ?00 ?00 m a typ v il = 2 v input capacitance 10 10 pf typ
rev. d ? ADUC812 ADUC812bs parameter v dd = 5 v v dd = 3 v unit test conditions/comments digital outputs output high voltage (v oh ) 2.4 2.4 v min v dd = 4.5 v to 5.5 v i source = 80 m a 4.0 2.6 v typ v dd = 2.7 v to 3.3 v i source = 20 m a output low voltage (v ol ) ale, psen , ports 0 and 2 0.4 0.4 v max i sink = 1.6 ma 0.2 0.2 v typ i sink = 1.6 ma port 3 0.4 0.4 v max i sink = 8 ma 0.2 0.2 v typ i sink = 8 ma floating state leakage current 10 10 m a max 1 1 m a typ floating state output capacitance 10 10 pf typ power requirements 14, 15, 16 i dd n ormal mode 17 43 25 ma ma x mclkin = 16 mhz 32 16 ma typ mclkin = 16 mhz 26 12 ma typ mclkin = 12 mhz 83 ma typ mclkin = 1 mhz i dd idle mode 25 10 ma max mclkin = 16 mhz 18 6 ma typ mclkin = 16 mhz 15 6 ma typ mclkin = 12 mhz 72 ma typ mclkin = 1 mhz i dd power-down mode 18 30 15 m a max 55 m a typ notes 1 specifications apply after calibration. 2 temperature range ?0 c to +85 c. 3 linearity is guaranteed during normal microconverter core operation. 4 linearity may degrade when programming or erasing the 640 byte flash/ee space during adc conversion times due to on-chip charge pump activity. 5 measured in production at v dd = 5 v after software calibration routine at 25 c only. 6 user may need to execute software calibration routine to achieve these specifications, which are configuration dependent. 7 the offset and gain calibration spans are defined as the voltage range of user system offset and gain errors that the ADUC812 c an compensate. 8 snr calculation includes distortion and noise components. 9 specification is not production tested, but is supported by characterization data at initial product release. 10 the temperature sensor will give a measure of the die temperature directly; air temperature can be inferred from this result. 11 dac linearity is calculated using: reduced code range of 48 to 4095, 0 to v ref range reduced code range of 48 to 3995, 0 to v dd range dac output load = 10 k w and 50 pf. 12 flash/ee memory performance specifications are qualified as per jedec specification (data retention) and jedec draft specificat ion a117 (endurance). 13 endurance cycling is evaluated under the following conditions: mode = byte programming, page erase cycling cycle pattern = 00h to ffh erase time = 20 ms program time = 100 m s 14 i dd at other mclkin frequencies is typically given by: normal mode (v dd = 5 v): i dd = (1.6 nas mclkin) + 6 ma normal mode (v dd = 3 v): i dd = (0.8 nas mclkin) + 3 ma idle mode (v dd = 5 v): i dd = (0.75 nas mclkin) + 6 ma idle mode (v dd = 3 v): i dd = (0.25 nas mclkin) + 3 ma where mclkin is the oscillator frequency in mhz and resultant i dd values are in ma. 15 i dd currents are expressed as a summation of analog and digital power supply currents during normal microconverter operation. 16 i dd is not measured during flash/ee program or erase cycles; i dd will typically increase by 10 ma during these cycles. 17 analog i dd = 2 ma (typ) in normal operation (internal v ref , adc, and dac peripherals powered on). 18 ea = port0 = dv dd , xtal1 (input) tied to dv dd , during this measurement. typical specifications are not production tested, but are supported by characterization data at initial product release. timing specifications?ee pages 46?5. specifications subject to change without notice. please refer to user guide, quick reference guide, application notes, and silicon errata sheet at www.analog.com/microconverter for additional information.
rev. d ADUC812 ? 52-lead mqfp 52 51 50 49 48 43 42 41 40 47 46 45 44 14 15 16 17 18 19 20 21 22 23 24 25 26 1 2 3 4 5 6 7 8 9 10 13 12 11 39 38 37 36 35 34 33 32 31 30 29 28 27 pin 1 identifier top view (not to scale) p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 dv dd dgnd p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ale psen ea p1.0/adc0/t2 p1.1/adc1/t2ex p1.2/adc2 p1.3/adc3 av dd agnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ ss p1.6/adc6 p2.7/a15/a23 p2.6/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dgnd dv dd xtal2 xtal1 p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/mosi p1.7/adc7 reset p3.0/rxd p3.1/txd p3.2/ int0 p3.3/ int1 /miso dv dd dgnd p3.4/t0 p3.5/t1/ convst p3.7/ rd sclock p3.6/ wr ADUC812 absolute maximum ratings * (t a = 25 c, unless otherwise noted.) av dd to dv dd . . . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v agnd to dgnd . . . . . . . . . . . . . . . . . . . . ?.3 v to +0.3 v dv dd to dgnd, av dd to agnd . . . . . . . . . ?.3 v to +7 v digital input voltage to dgnd . . . ?.3 v to dv dd + 0.3 v digital output voltage to dgnd . . ?.3 v to dv dd + 0.3 v v ref to agnd . . . . . . . . . . . . . . . . . ?.3 v to av dd + 0.3 v analog inputs to agnd . . . . . . . . . . ?.3 v to av dd + 0.3 v operating temperature range industrial (b version) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 c to +85 c caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ADUC812 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. 56-lead lfcsp pin 1 indentifier ADUC812 top view (not to scale) p1.1/adc1/ t2ex p1.2/adc2 p1.3/adc3 1 2 3 4 5 6 7 8 9 11 12 13 18 19 20 21 22 25 10 14 15 16 17 23 24 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 av dd av dd agnd agnd c ref v ref dac0 dac1 p1.4/adc4 p1.5/adc5/ ss p1.6/adc6 agnd p1.7/adc7 reset p3.0/rxd p3.1/txd p2.7/a15/a23 p2.6/a14/a22 p2.5/a13/a21 p2.4/a12/a20 dv dd xtal2 xtal1 dgnd dgnd p2.3/a11/a19 p2.2/a10/a18 p2.1/a9/a17 p2.0/a8/a16 sdata/ mosi sclock p3.7/ rd p3.6/ wr p3.5/t1/ convst p3.4/t0 dgnd dv dd p3.3/ int1 /miso p3.2/ int0 p1.0/adc0/ t2 p0.7/ad7 p0.6/ad6 p0.5/ad5 p0.4/ad4 dv dd dgnd p0.3/ad3 p0.2/ad2 p0.1/ad1 p0.0/ad0 ale psen ea ordering guide temperature package package model range description option ADUC812bs ?0 c to +85 c 52-lead plastic quad flatpack s-52 ADUC812bs ?0 c to +85 c 56-lead chip scale package cp-56 eval-ADUC812qs quickstart development system eval-ADUC812qsp quickstart development system plus pin configurations storage temperature range . . . . . . . . . . . . ?5 c to +150 c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c q ja thermal impedance . . . . . . . . . . . . . . . . . . . . . . . 90 c/w lead temperature, soldering vapor phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . . 215 c infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 220 c * stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability.
rev. d ADUC812 ? pin function descriptions mnemonic type function dv dd pd igital positive supply voltage, 3 v or 5 v nominal. av dd pa nalog positive supply voltage, 3 v or 5 v nominal. c ref id ecoupling input for on-chip reference. connect 0.1 m f between this pin and agnd. v ref i/o reference input/output. this pin is connected to the internal reference through a series resistor and is the reference source for the adc. the nominal internal reference voltage is 2.5 v, which appears at the pin. this pin can be overdriven by an external reference. agnd g analog ground. ground reference point for the analog circuitry. p1.0?1.7 i port 1 is an 8-bit input port only. unlike other ports, port 1 defaults to analog input mode. to configure any of these port pins as a digital input, write a 0 to the port bit. port 1 pins are multifunctional and share the following functionality. adc0?dc7 i analog inputs. eight single-ended analog inputs. channel selection is via adccon2 sfr. t2 i timer 2 digital input. input to timer/counter 2. when enabled, counter 2 is incremented in response to a 1 to 0 transition of the t2 input. t2ex i digital input. capture/reload trigger for counter 2; also functions as an up/down control input for counter 2. ss i slave select input for the spi interface. sdata i/o user selectable, i 2 c compatible or spi data input/output pin. sclock i/o serial clock pin for i 2 c compatible or spi serial interface clock. mosi i/o spi master output/slave input data i/o pin for spi interface. miso i/o spi master input/slave output data i/o pin for spi serial interface. dac0 o voltage output from dac0. dac1 o voltage output from dac1. reset i digital input. a high level on this pin for 24 master clock cycles while the oscillator is running resets the device. external power-on reset (por) circuity must be implemented to drive the reset pin as described in the power-on reset operation section. p3.0?3.7 i/o port 3 is a bidirectional port with internal pull-up resistors. port 3 pins that have 1s written to them are pulled high by the internal pull-up resistors; in that state they can be used as inputs. as inputs, port 3 pins being pulled externally low will source current because of the internal pull-up resistors. port 3 pins also contain various secondary functions that are described below. rxd i/o receiver data input (asynchronous) or data input/output (synchronous) of serial (uart) port txd o transmitter data output (asynchronous) or clock output (synchronous) of serial (uart) port int0 i interrupt 0, programmable edge or level triggered interrupt input, int0 can be programmed to one of two priority levels. this pin can also be used as a gate control input to timer 0. int1 i interrupt 1, programmable edge or level triggered interrupt input, int1 can be programmed to one of two priority levels. this pin can also be used as a gate control input to timer 1. t0 i timer/counter 0 input. t1 i timer/counter 1 input. convst i active low convert start logic input for the adc block when the external convert start function is enabled. a low-to-high transition on this input puts the track-and-hold into its hold mode and starts conversion. wr ow rite control signal, logic output. latches the data byte from port 0 into the external data memory. rd or ead control signal, logic output. enables the external data memory to port 0. xtal2 o output of the inverting oscillator amplifier. xtal1 i input to the inverting oscillator amplifier and to the internal clock generator circuits. dgnd g digital ground. ground reference point for the digital circuitry. p2.0?2.7 i/o port 2 is a bidirectional port with internal pull-up resistors. port 2 pins that have 1s written to them are (a8?15) pulled high by the internal pull-up resistors; in that state they can be used as inputs. as inputs, port 2 (a16?23) pins being pulled externally low will source current because of the internal pull-up resistors. port 2 emits the high order address bytes during fetches from external program memory and middle and high order address bytes during accesses to the external 24-bit external data memory space.
rev. d ADUC812 ? mnemonic type function psen op rogram store enable, logic output. this output is a control signal that enables the external program memory to the bus during external fetch operations. it is active every six oscillator periods except during external data memory accesses. this pin remains high during internal program execution. psen can also be used to enable serial download mode when pulled low through a resistor on power-up or reset. ale o address latch enable, logic output. this output is used to latch the low byte (and page byte for 24-bit address space accesses) of the address into external memory during normal operation. it is activated every six oscillator periods except during an external data memory access. ea ie xternal access enable, logic input. when held high, this input enables the device to fetch code from internal program memory locations 0000h to 1fffh. when held low, this input enables the device to fetch all instructions from external program memory. p0.7?0.0 i/o port 0 is an 8-bit open-drain bidirectional i/o port. port 0 pins that have 1s written to them float and in (a0?7) that state can be used as high impedance inputs. port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. in this application, it uses strong internal pull-ups when emitting 1s. terminology adc specifications integral nonlinearity this is the maximum deviation of any code from a straight line passing through the endpoints of the adc transfer function. the endpoints of the transfer function are zero scale, a point 1/2 lsb below the first code transition, and full scale, a point 1/2 lsb above the last code transition. differential nonlinearity this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. offset error this is the deviation of the first code transition (0000 . . . 000) to (0000 ... 001) from the ideal, i.e., +1/2 lsb. full-scale error this is the deviation of the last code transition from the ideal ain voltage (full scale ?1.5 lsb) after the offset error has been adjusted out. signal-to-(noise + distortion) ratio this is the measured ratio of signal-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fun- damental. noise is the rms sum of all nonfundamental signals up to half the sampling frequency (f s /2), excluding dc. the ratio is dependent upon the number of quantization levels in the digiti- zation process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by: signal-to- ( noise + distortion ) = (6.02 n + 1.76) db thus for a 12-bit converter, this is 74 db. total harmonic distortion total harmonic distortion is the ratio of the rms sum of the harmonics to the fundamental. dac specifications relative accuracy relative accuracy or endpoint linearity is a measure of the maximum deviation from a straight line passing through the endp oints of the dac transfer function. it is measured after adjusting for zero-scale error and full-scale error. voltage output settling time this is the amount of time it takes for the output to settle to a specified level for a full-scale input change. digital-to-analog glitch impulse this is the amount of charge injected into the analog output when the inputs change state. it is specified as the area of the glitch in nv sec. pin function descriptions (continued)
rev. d ADUC812 ? architecture, main features the ADUC812 is a highly integrated, true 12-bit data acquisi- tion system. at its core, the ADUC812 incorporates a high perfor mance 8-bit (8052 compatible) mcu with on-chip reprogrammable nonvolatile flash program memory control- ling a multichannel ( eight i nput channels) 12-bit adc. the chip incorporates all secondary functions to fully support t he programmable data acquisition core. these secondary functions include user flash memory, watchdog timer (wdt), power supply monitor (psm), and various industry- standard parallel and serial interfaces. external program memory space ffffh 2000h 1fffh 0000h ea = 0 external program memory space ea = 1 internal 8k byte flash/ee program memory program memory space read only accessible by indirect addressing only accessible by direct and indirect addressing special function registers accessible by direct addressing only 640 bytes flash/ee data memory accessed indirectly via sfr control registers internal data memory space ffh 80h 7fh 00h upper 128 lower 128 ffh 80h external data memory space (24-bit address space) ffffffh 000000h data memory space read/write (page 159) (page 0) 00h 9fh figure 1. program and data memory maps t he l ower 128 bytes of internal data memory are mapped as shown in figure 2. the lowest 32 bytes are grouped into four banks of eight registers addressed as r0 through r7. the next 16 b ytes (128 bits) above the register banks form a block of bit addressable memory space at bit addresses 00h through 7fh. bit addressable space (bit addresses 0fh?fh) 4 banks of 8 registers r0?7 banks selected via bits in psw 11 10 01 00 07h 0fh 17h 1fh 2fh 7fh 00h 08h 10h 18h 20h reset value of stack pointer figure 2. lower 128 bytes of internal ram memory organization as with all 8052 compatible devices, the ADUC812 has separate address spaces for program and data memory as shown in fig- ure 1. also as shown in figure 1, an additional 640 bytes of user data flash eeprom are available to the user. the user data flash memory area is accessed indirectly via a group of control registers mapped in the special function register (sfr) area in the data memory space. t he sfr space is mapped in the upper 128 bytes of internal data memory space. the sfr area is accessed by direct addressing only and provides an interface between the cpu and all on-chip peripherals. a block diagram showing the programming model of the ADUC812 via the sfr area is shown in figure 3. 128-byte special function register area 8k byte electrically reprogrammable nonvolatile flash/ee program memory 8051 compatible core other on-chip peripherals temperature sensor 2 12-bit dacs serial i/o parallel i/o wdt psm autocalibrating 8-channel high speed 12-bit adc 640-byte electrically reprogrammable nonvolatile flash/ee data memory figure 3. programming model
rev. d ADUC812 ?0 overview of mcu-related sfrs accumulator sfr acc is the accumulator register and is used for math opera- tions including addition, subtraction, integer multiplication and division, and boolean bit manipulations. the mnemonics for accumulator-specific instructions refer to the accumulator as a. b sfr the b register is used with the acc for multiplication and division operations. for other instructions, it can be treated as a general-purpose scratch pad register. stack pointer sfr the sp register is the stack pointer and is used to hold an internal ram address that is called the ?op of the stack.?the sp register is incremented before data is stored during push and call executions. while the stack may reside anywhere in on-chip ram, the sp register is initialized to 07h after a reset. this causes the stack to begin at location 08h. data pointer the data pointer is made up of three 8-bit registers: dpp (page byte), dph (high byte), and dpl (low byte). these are used to provide memory addresses for internal and external code access and external data access. it may be manipulated as a 16-bit register (dptr = dph, dpl), although inc dptr instruc tions will automatically carry over to dpp, or as three independent 8- bit registers (dpp, dph, and dpl). program status word sfr the psw register is the program status word that contains several bits reflecting the current status of the cpu as detailed in table i. sfr address d0h power-on default value 00h bit addressable yes y cc a0 f1 s r0 s rv o1 fp table i. psw sfr bit designations bit name description 7c yc arry flag 6a ca uxiliary carry flag 5f 0g eneral-purpose flag 4 rs1 register bank select bits 3 rs0 rs1 rs0 selected bank 000 011 102 113 2o vo verflow flag 1f 1g eneral-purpose flag 0p parity bit power control sfr the power control (pcon) register contains bits for power saving options and general-purpose status flags as shown in table ii. sfr address 87h power-on default value 00h bit addressable no d o m sd p i r e sd p o t n if f o e l a1 f g0 f gd pl d i table ii. pcon sfr bit designations bit name description 7 smod double uart baud rate 6 reserved 5 reserved 4 aleoff disable ale output 3 gf1 general-purpose flag bit 2 gf0 general-purpose flag bit 1p dp ower-down mode enable 0 idl idle mode enable
rev. d ADUC812 ?1 special function registers all registers except the program counter and the four general-purpose register banks reside in the special function register (s fr) area. the sfr registers include control, configuration, and data registers that provide an interface between the cpu and other on-chi p peripherals. figure 4 shows a full sfr memory map and sfr contents on reset. unoccupied sfr locations are shown dark shaded (not used). unoccupied locations in the sfr address space are not implemented, i.e., no register exists at this location. if an unoccupied location is read, an unspecified value is returned. sfr locations reserved for on-chip testing are shown lighter shaded (reserv ed) and should not be accessed by user software. sixteen of the sfr locations are also bit addressable and denoted by ? i.e., the bit addressable sfrs are those whose address ends in 0h or 8h. spicon 1 f8h 00h dac0l f9h 00h dac0h fah 00h dac1l fbh 00h dac1h fch 00h daccon fdh 04h reserved not used b 1 f0h 00h adco fsl 2 f1h 00h adco fsh 2 f2h 20h adcgainl 2 f3h 00h adcgainh 2 f4h 00h adccon3 f5h 00h reserved i2ccon 1 e8h 00h reserved acc 1 e0h 00h reserved adccon2 1 d8h 00h adcd atal d9h 00h adcdat ah dah 00h reserved psw 1 d0h 00h dmal d2h 00h dmah d3h 00h dmap d4h 00h reserved t2con 1 c8h 00h rcap2l cah 00h rcap2h cbh 00h tl2 cch 00h th2 cdh 00h reserved wdcon 1 c0h 00h ip 1 b8h 00h econ b9h 00h etim1 bah 52h etim2 bbh 04h edata1 bch 00h edata2 bdh 00h not used ie 1 a8h 00h ie2 a9h 00h not used p2 1 a0h ffh not used scon 1 98h 00h sbuf 99h 00h not used p1 1, 3 90h ffh not used tcon 1 88h 00h tmod 89h 00h tl0 8ah 00h tl1 8bh 00h th0 8ch 00h th1 8dh 00h not used p0 1 80h ffh sp 81h 07h dpl 82h 00h dph 83h 00h dpp 84h 00h reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved not used not used not used not used not used not used not used not used not used not used not used p3 1 b0h ffh not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used not used spidat f7h 00h adccon1 efh 20h reserved psmcon dfh deh edarl c6h 00h edata3 beh 00h edata4 bfh 00h not used not used pcon 87h 00h ispi ffh 0 wcol feh 0 spe fdh 0 spim fch 0 cpol fbh 0 cpha fah spr1 f9h 0 spr0 f8h 0 bits f7h 0 f6h 0 f5h 0 f4h 0 f3h 0 f2h f1h 0 f0h 0 bits mdo efh 0 mde eeh 0 mco edh 0 ech 0 i2cm ebh 0 eah e9h 0 e8h 0 bits e7h 0 e6h 0 e5h 0 e4h 0 e3h 0 e2h e1h 0 e0h 0 bits adci dfh 0 dma deh 0 cconv ddh 0 sconv dch 0 cs3 dbh 0 cs2 dah cs1 d9h 0 cs0 d8h 0 bits cy d7h 0 ac d6h 0 f0 d5h 0 rs1 d4h 0 rs0 d3h 0 ov d2h fi d1h 0 p d0h 0 bits tf2 cfh 0 exf2 ceh 0 rclk cdh 0 tclk cch 0 exen2 cbh 0 tr2 cah cnt2 c9h 0 cap2 c8h 0 bits pre2 c7h 0 pre1 c6h 0 pre0 c5h 0 c4h 0 wdr1 c3h 0 wdr2 c2h wds c1h 0 wde c0h 0 bits psi bfh 0 padc beh 0 pt2 bdh 0 ps bch 0 pt1 bbh 0 px1 bah pt0 b9h 0 px0 b8h 0 bits rd b7h 1 wr b6h 1 t1 b5h 1 t0 b4h 1 int1 b3h 1 int0 b2h txd b1h 1 rxd b0h 1 bits ea afh eadc aeh et2 adh es ach 0 et1 abh 0 ex1 aah et0 a9h 0 ex0 a8h 0 bits a7h a6h a5h 1 a4h 1 a3h 1 a2h a1h 1 a0h 1 bits sm0 9fh 0 sm1 9eh 0 sm2 9dh 0 ren 9ch 0 tb8 9bh 0 rb8 9ah ti 99h 0 ri 98h 0 bits 97h 1 96h 1 95h 1 94h 1 93h 1 92h t2ex 91h 1 t2 90h 1 bits tf1 8fh 0 tr1 8eh 0 tf0 8dh 0 tr0 8ch 0 ie1 8bh 0 it1 8ah ie0 89h 0 it0 88h 0 bits 87h 1 86h 1 85h 1 84h 1 83h 1 82h 81h 1 80h 1 bits 1 1 0 1 0 1 ie0 89h 0 it0 88h 0 tcon 88h 00h mnemonic sfr address default value mnemonic default value sfr address these bits are contained in this byte. sfr map key: sfr notes 1 sfrs whose address ends in 0h or 8h are bit addressable. 2 calibration coefficients are preconfigured on power-up to factory calibrated values. 3 the primary function of port 1 is as an analog input port; therefore, to enable the digital secondary functions on these port pins, write a ?? to the corresponding port 1 sfr bit. 0 reserved reserved reserved etim3 c4h c9h 0 0 0 0 0 0 0 0 0 0 00 11 i2cdat 9ah 00h i2cadd 9bh 55h mdi i2crs i2ctx i2ci figure 4. special function register locations and reset values
rev. d ADUC812 ?2 adc circuit information general overview the adc conversion block incorporates a fast, 8-channel, 12-bit, single-supply adc. this block provides the user with multichannel mux, track-and-hold, on-chip reference, calibra- tion features, and adc. all components in this block are easily configured via a 3-register sfr interface. th e adc consists of a conventional successive-a pproxima tion converter based around a capacitor dac. the converter accepts an analog input range of 0 v to v ref . a high precision, low drift and factory calibrated 2.5 v reference is provided on-chip. the internal reference may be overdriven via the external v ref pin. this external reference can be in the range 2.3 v to av dd . single step or continuous conversion modes can be initiated in software or alternatively by applying a convert signal to an e xternal pin. timer 2 can also be configured to generate a repetitive trigger for adc conversions. the adc may be configured to operate in a dma mode w hereby the adc block continuously converts and captures samples to an external ram space without any interaction from the mcu core. this automatic capture facility can extend through a 16 mbyte external data memory space. the ADUC812 is shipped with factory programmed calibration coefficients that are automatically downloaded to the adc on power-up, ensuring optimum adc performance. the adc core contains internal offset and gain calibration registers. a software calibration routine is provided to allow the user to overwrite the factory programmed calibration coefficients if required, thus minimizing the impact of endpoint errors in the user? target system. a voltage output from an on-chip band gap reference propor- tional to absolute temperature can also be routed through the front end adc multiplexer (effectively a ninth adc channel input) facilitating a temperature sensor implementation. adc transfer function the analog input range for the adc is 0 v to v ref . for this r ange, the designed code transitions occur midway between successive integer lsb values (i.e., 1/2 lsb, 3/2 lsbs, 5/2 lsbs . . . fs ?/2 lsbs). the output coding is straight binary with 1 lsb = fs/4096 or 2.5 v/4096 = 0.61 mv when v ref = 2.5 v. the ideal input/output transfer characteristic for the 0 to v ref range is shown in figure 5. output code 111...111 111...110 111...101 111...100 000...011 000...010 000...001 000...000 0v 1lsb +fs ?lsb voltage input 1lsb = fs 4096 figure 5. adc transfer function typical operation once configured via the adccon 1? sfrs (shown on the following page), the adc will convert the analog input and pro vide an adc 12-bit result word in the adcdatah/l sfrs. the top four bits of the adcdatah sfr will be written with the channel selection bits to identify the channel result. the format of the adc 12-bit result word is shown in figure 6. ch?d top 4 bits high 4 bits of adc result word low 8 bits of the adc result word adcdatah sfr adcdatal sfr figure 6. adc result format
rev. d ADUC812 ?3 adccon1?adc control sfr #1) the adccon1 register controls conversion and acquisition times, hardware conversion modes and power-down modes as detailed below. sfr address efh sfr power-on default value 20h table iii. adccon1 sfr bit designations bit name description adccon1.7 md1 the mode bits (md1, md0) select the active operating mode of the adc as follows: adccon1.6 md0 md1 md0 active mode 00 adc powered down 01 adc normal mode 10 adc powered down if not executing a conversion cycle 11 adc standby if not executing a conversion cycle note: in power-down mode the adc v ref circuits are maintained on, whereas all adc peripherals are powered down, thus minimizing current consumption. adccon1.5 ck1 the adc clock divide bits (ck1, ck0) select the divide ratio for the master clock used to generate the adccon1.4 ck0 adc clock. a typical adc conversion will require 17 adc clocks. the divider ratio is selected as follows: ck1 ck0 mclk divider 001 012 104 118 adccon1.3 aq1 the adc acquisition select bits (aq1, aq0) select the time provided for the input track-and-hold adccon1.2 aq0 amplifier to acquire the input signal, and are selected as follows: aq1 aq0 #adc clks 001 012 104 118 adccon1.1 t2c the timer 2 conversion bit (t2c) is set by the user to enable the timer 2 overflow bit be used as the adc convert start trigger input. adc conversions are initiated on the second timer 2 overflow. adccon1.0 exc the external trigger enable bit (exc) is set by the user to allow the external convst pin to be used as the active low convert start input. this input should be an active low pulse (minimum pulsewidth >100 ns) at the required sample rate. 1 d m0 d m1 k c0 k c1 q a0 q ac 2 tc x e
rev. d ADUC812 ?4 adccon2?adc control sfr #2) the adccon2 register controls adc channel selection and conversion modes as detailed below. sfr address d8h sfr power-on default value 00h i c d aa m dv n o c cv n o c s3 s c2 s c1 s c0 s c table iv. adccon2 sfr bit designations l ocation name description adccon2.7 adci the adc interrupt bit (adci) is set by hardware at the end of a single adc conversion cycle or at the end of a dma block conversion. adci is cleared by hardware when the pc vectors to the adc interrupt service routine. adccon2.6 dma the dma mode enable bit (dma) is set by the user to enable a preconfigured adc dma mode operation. a more detailed description of this mode is given in the adc dma mode section. adccon2.5 cconv the continuous conversion bit (cconv) is set by the user to initiate the adc into a continuous mode of conversion. in this mode, the adc starts converting based on the timing and channel configuration already set up in the adccon sfrs; the adc automatically starts another conversion once a previous conversion has completed. adccon2.4 sconv the single conversion bit (sconv) is set to initiate a single conversion cycle. the sconv bit is automatically reset to ??on completion of the single conversion cycle. adccon2.3 cs3 the channel selection bits (cs3?) allow the user to program the adc channel selection under adccon2.2 cs2 software control. when a conversion is initiated, the channel converted will be the one pointed to by adccon2.1 cs1 these channel selection bits. in dma mode, the channel selection is derived from the channel id adccon2.0 cs0 written to the external memory. cs3 cs2 cs1 cs0 ch# 00000 00011 00102 00113 01004 01015 01106 01117 1000temp sensor 1111 dma stop all other combinations reserved. adccon3?adc control sfr #3) the adccon3 register gives user software an indication of adc busy status. sfr address f5h sfr power-on default value 00h y s u bd v s rd v s rd v s rd v s rd v s rd v s rd v s r table v. adccon3 sfr bit designations bit location bit status description adccon3.7 busy the adc busy status bit (busy) is a read-only status bit that is set during a valid adc conversion or calibration cycle. busy is automatically cleared by the core at the end of conversion or calibration. adccon3.6 rsvd adccon3.0?.6 are reserved (rsvd) for internal use. these bits will read as ??and should only adccon3.5 rsvd be written as ??by user software. adccon3.4 rsvd adccon3.3 rsvd adccon3.2 rsvd adccon3.1 rsvd adccon3.0 rsvd
rev. d ADUC812 ?5 driving the adc the adc incorporates a successive approximation (sar) archi- tecture involving a charge-sampled input stage. figure 7 shows the equivalent circuit of the analog input section. each adc conversion is divided into two distinct phases as defined by the position of the switches in figure 7. during the sampling phase (with sw1 and sw2 in the ?rack?position), a charge propor- tional to the voltage on the analog input is developed across the input sampling capacitor. during the conversion phase (with both switches in the ?old?position), the capacitor dac is adjusted via internal sar logic until the voltage on node a is zero, indicating that the sampled charge on the input capacitor is balanced out by the charge being output by the capacitor dac. the digital value finally contained in the sar is then latched out as the result of the adc conversion. control of the sar, a nd timing of acquisition and sampling modes, is handled a utomatically by built-in adc control logic. acquisition and conversion times are also fully configurable under user control. ADUC812 temperature sensor adc0 adc7 200 sw1 2pf node a comparator sw2 hold track track hold capacitor dac agnd figure 7. internal adc structure note that whenever a new input channel is selected, a residual charge from the 2 pf sampling capacitor places a transient on the newly selected input. the signal source must be capable of recovering from this transient before the sampling switches click into ?old?mode. delays can be inserted in software (between channel selection and conversion request) to account for input stage settling, but a hardware solution will alleviate this burden from the software design task and will ultimately result in a cleaner system implementation. one hardware solution would be to choose a very fast settling op amp to drive each analog input. such an op amp would need to settle fully from a small s ignal transient in less than 300 ns to guarantee adequate settling under all software configurations. a better solution, recommended for use with any amplifier, is shown in figure 8. though at first glance the circuit in figure 8 may look like a simple antialiasing filter, it actually serves no such purpose since its corner frequency is well above the nyquist frequency, even at a 200 khz sample rate. though the r/c does help to reject some incoming high frequency noise, its primary function is to ensure that the transient demands of the adc input stage are met. it does so by providing a capacitive bank from which the 2 pf ADUC812 adc0 1 0.01 f 51 figure 8. buffering analog inputs sampling capacitor can draw its charge. since the 0.01 m f capacitor in figure 8 is more than 4096 times the size of the 2 pf sampling capacitor, its voltage will not change by more than one count (1/4096) of the 12-bit transfer function when the 2 pf charge from a previous channel is dumped onto it. a larger capacitor can be used if desired, but not a larger resistor (for reasons described below). the schottky diodes in figure 8 may be necessary to limit the voltage applied to the analog input pin as per the absolute maxi- mum ratings. they are not necessary if the op amp is powered from the same supply as the ADUC812 since in that case, the op amp is unable to generate voltages above v dd or below ground. an op amp is necessary unless the signal source is very low imped- ance to begin with. dc leakage cur rents at the ADUC812? analog inputs can cause measurable dc errors with external source imped- ances of as little as 100 w . to ensure accu rate adc operation, keep the total source impedance at each analog input less than 61 w . the table below illustrates ex amples of how source impedance can affect dc accuracy. source error from 1 a error from 10 a impedance leakage current leakage current 61 w 61 m v = 0.1 lsb 610 m v = 1 lsb 610 w 610 m v = 1 lsb 61 mv = 10 lsb although figure 8 shows the op amp operating at a gain of 1, you can configure it for any gain needed. also, you can use an instrumentation amplifier in its place to condition differential signals. use any modern amplifier that is capable of delivering the signal (0 to v ref ) with minimal saturation. some single- supply, rail-to-rail op amps that are useful for this purpose include, but are not limited to, the ones given in table vi. check analog devices literature (cd rom data book, and so on) for details about these and other op amps and instrumentation amps. table vi. some single-supply op amps op amp model characteristics op181/op281/op481 micropower op191/op291/op491 i/o good up to v dd , low cost op196/op296/op496 i/o to v dd , micropower, low cost op183/op283 high gain-bandwidth product op162/op262/op462 high gbp, micro package ad820/ad822/ad824 fet input, low cost ad823 fet input, high gbp keep in mind that the adc? transfer function is 0 v to v ref , and any signal range lost to amplifier saturation near ground will impact dynamic range. though the op amps in table vi are capable of delivering output signals very closely approaching ground, no amplifier can deliver signals all the way to ground when powered by a single supply. therefore, if a negative supply is available, consider using it to power the front end amplifiers.
rev. d ADUC812 ?6 however, be sure to include the schottky diodes shown in figure 8 (or at least the lower of the two diodes) to protect the analog input from undervoltage conditions. to summarize this section, use the circuit of figure 8 to drive the analog input pins of the ADUC812. voltage reference connections the on-chip 2.5 v band gap voltage reference can be used as the reference source for the adc and dacs. to ensure the accuracy of the voltage reference, decouple both the v ref pin and the c ref pin to ground with 0.1 m f ceramic chip capacitors as shown in figure 9. 0.1 f 0.1 f v ref c ref bu ffer 51 2.5v b and gap reference ADUC812 bu ffer figure 9. decoupling v ref and c ref the internal voltage reference can also be tapped directly from the v ref pin, if desired, to drive external circuitry. however, a buffer must be used to ensure that no current is drawn from the v ref pin itself. the voltage on the c ref pin is that of an internal node within the buffer block, and its voltage is critical to adc and dac accuracy. do not connect anything to this pin except the capacitor, and be sure to keep trace-lengths short on the c ref capacitor, decoupling the node straight to the underlying ground plane. the ADUC812 powers up with its internal voltage reference in the ?ff?state. the voltage reference turns on automatically whenever the adc or either dac gets enabled in software. once enabled, the voltage reference requires approximately 65 ms to power up and settle to its specified value. be sure that your software allows this time to elapse before initiating any conversions. if an external voltage reference is preferred, connect it to the v ref pin as shown in figure 10 to overdrive the internal reference. to ensure accurate adc operation, the voltage applied to v ref must be between 2.3 v and av dd . in situations where analog input signals are proportional to the power supply (such as some strain gage applications), it may be desirable to connect the v ref pin directly to av dd . in such a configuration, the user must also connect the c ref pin directly to av dd to circumvent internal buffer headroom limitations. this allows the adc input transfer function to span the full range of 0 v to av dd accurately. operation of the adc or dacs with a reference voltage below 2.3 v, however, may incur loss of accuracy resulting in missing codes or nonmonotonicity. for that reason, do not use a reference voltage less than 2.3 v. v dd external vo ltag e reference v ref c ref bu ffer 51 2.5v b and gap reference ADUC812 0.1 f 0.1 f figure 10. using an external voltage reference configuring the adc the three sfrs (adccon1, adccon2, adccon3) con- figure the adc. in nearly all cases, an acquisition time of one a dc clock (adccon1.2 = 0, adccon1.3 = 0) will provide plenty of time for the ADUC812 to acquire its signal before switching the internal track-and-hold amplifier into hold mode. the only exception would be a high source impedance analog input, but these should be buffered first anyway since source impedances of greater than 610 w can cause dc errors as well. the ADUC812? successive approximation adc is driven by a divided down version of the master clock. to ensure adequate adc operation, this adc clock must be between 400 khz and 4 mhz, and optimum performance is obtained with adc clock between 400 khz and 3 mhz. frequencies within this range can be achieved with master clock frequencies from 400 khz to well above 16 mhz with the four adc clock divide ratios to choose from. for example, with a 12 mhz master clock, set the adc clock divide ratio to 4 (i.e., adcclk = mclk/4 = 3 mhz) by setting the appropriate bits in adccon1 (adccon1.5 = 1, adccon1.4 = 0). the total adc conversion time is 15 adc clocks, plus one adc clock for synchronization, plus the selected acquisition tim e (1, 2, 3, or 4 adc clocks). for the example above, with a one clock acquisition time, total conversion time is 17 adc clocks (or 5.67 m s for a 3 mhz adc clock). in continuous conversion mode, a new conversion begins each time the previous one finishes. the sample rate is the inverse of the total conversion time described above. in the example above, the continuous conversion mode sample rate would be 176.5 khz. adc dma mode the on-chip adc has been designed to run at a maximum conversion speed of 5 m s (200 khz sampling rate). when con- verting at this rate, the ADUC812 microconverter has 5 m s to read the adc result and store the result in memory for further postprocessing, otherwise the next adc sample could be lost. in an interrupt driven routine, the microconverter would also have to jump to the adc interrupt service routine, which will also increase the time required to store the adc results. in applications where the ADUC812 cannot sustain the interrupt rate, an adc dma mode is provided. to enable dma mode, bit 6 in adccon2 (dma) must be set. this allows the adc results to be written directly to a 16 mbyte external static memory sram (mapped into data memory space)
rev. d ADUC812 ?7 without any interaction from the ADUC812 core. this mode allows the ADUC812 to capture a contiguous sample stream at full adc update rates (200 khz). dma mode configuration example to set the ADUC812 into dma mode, a number of steps must be followed. 1. the adc must be powered down by setting md1 and md0 to 0 in adccon1. 2. the dma address pointer must be set to the start address of wh e re the adc results are to be written. this is done by writing to the dma mode address pointers dmal, dmah, and dmap. dmal must be written to first, followed by dmah, and then dmap. 3. the external memory must be preconfigured. this consists of writing the required adc channel ids into the top four bits of every second memory location in the external sram, starting at the first address specified by the dma address pointer. as the adc dma mode operates independently of the ADUC812 core, it is necessary to provide it with a stop command. this is done by duplicating the last channel id to be converted, fol- lowed by ?111?into the next channel selection field. figure 11 shows a typical preconfiguration of external memory. 1111 0011 0011 100 0 010 1 0010 00000ah 000000h stop command repeat last channel for a valid stop condition convert adc ch#3 convert temp sensor convert adc ch#5 convert adc ch#2 figure 11. ty pical dma external memory preconfiguration 4. the dma is initiated by writing to the adc sfrs in the following sequence. a. adccon2 is written to enable the dma mode, i.e., mov adccon2, #40h; dma mode enabled. b. adccon1 is written to configure the conversion time and power-up of the adc. it can also enable timer 2 driven c onversions or external triggered conversions if required. c. adc conversions are initiated by starting single/continuous conversions, starting timer 2 running for timer 2 conver- sions, or by receiving an external trigger. when the dma conversions are completed, the adc interrupt bit adci is set by hardware and the external sram contains the new adc conversion results as shown in figure 12. it should be noted that no result is written to the last two memory locations. when the dma mode logic is active, it is responsible for storing the adc results away from both the user and ADUC812 core logic. as it writes the results of the adc conversions to external memory, it takes over the external memory interface from the core. thus, any core instructions that access the external memory while dma mode is enabled will not gain access to it. the core will execute the instructions and they will take the same time to execute, but they will not gain access to the external memory. no conversion result written here conversion result for adc ch#3 conversion result for temp sensor conversion result for adc ch#5 conversion result for adc ch#2 1111 0011 0011 100 0 010 1 0010 00000ah 000000h stop command figure 12. typical external memory configuration post adc dma operation the dma logic operates from the adc clock and uses pipelining to perform the adc conversions and access th e external memory at the same time. the time it takes to perform one adc conver- sion is called a dma cycle. the actions performed by the logic during a typical dma cycle are shown in figure 13. write adc result converted during previous dma cycle read channel id to be converted during next dma cycle convert channel read during previous dma cycle dma cycle figure 13. dma cycle from the previous diagram, it can be seen that during one dma c ycle the following actions are performed by the dma logic. 1. an adc conversion is performed on the channel whose id was read during the previous cycle. 2. the 12-bit result and the channel id of the conversion per- formed in the previous cycle are written to the external memory. 3. the id of the next channel to be converted is read from external memory. for the previous example, the complete flow of events is shown in figure 13. because the dma logic uses pipelining, it takes three cycles before the first correct result is written out. micro operation during adc dma mode during adc dma mode, the microconverter core is free to continue code execution, including general housekeeping and communication tasks. however, it should be noted that mcu core accesses to ports 0 and 2 (which are being used by the dma controller) are gated off during adc dma mode of operation. this means that even though the instruction that accesses the external ports 0 or 2 will appear to execute, no data will be seen at these external ports as a result. t he microconverter core can be configured with an interrupt to be triggered by the dma controller when it has finished filling the requested block of ram with adc results, allowing the service routine for this interrupt to postprocess data without any real-time timing constraints. offset and gain calibration coefficients the ADUC812 has two adc calibration coefficients, one for offset calibration and one for gain calibration. both the offset and gain calibration coefficients are 14-bit words, located in the special function register (sfr) area. the offset calibration coefficient is divided into adcofsh (six bits) and adcofsl (eight bits),
rev. d ADUC812 ?8 and the gain calibration coefficient is divided into adcgainh (six bits) and adcgainl ( eight bits). the offset calibration coefficient com pensates for dc offset errors in both the adc and the input signal. increasing the offset coefficient compensates for positive offset, and effectively pushes the adc transfer function down. de- creasing the offset coefficient compensates for negative offset, and effectively pushes the adc transfer function up. the maximum offset that can be compensated is typically 5% of v ref , which equates to typically 125 mv with a 2.5 v reference. similarly, the gain calibration coefficient compensates for dc gain errors in both the adc and the input signal. increasing the gain coefficient compensates for a smaller analog input signal range and scales the adc transfer function up, effectively increasing the slope of the transfer function. decreasing the gain coefficient compensates for a larger analog input signal range and scales the adc transfer function down, effectively decreasing the slope of the transfer function. the maximum analog input signal range for which the gain coefficient can compensate is 1.025 v ref , and the minimum input range is 0.975 v ref , which equates to 2.5% of the reference voltage. calibration each ADUC812 is calibrated in the factory prior to shipping, and the offset and gain calibration coefficients are stored in a hidden area of flash/ee memory. each time the ADUC812 powers up, an internal power-on configuration routine copies these coefficients into the offset and gain calibration registers in the sfr area. the microconverter adc accuracy may vary from system to system due to board layout, grounding, clock speed, and so on. to get the best adc accuracy in your system, perform the software calibration routine described in application note uc005, available from the microconverter homepage at www.analog.com/microconverter. nonvolatile flash memory flash memory overview the ADUC812 incorporates flash memory technology on-chip to provide the user with a nonvolatile, in-circuit reprogrammable code and data memory space. flash/ee memory is a relatively new type of nonvolatile memory technology based on a single transistor cell architecture. this technology is basically an outgrowth of eprom technology and was developed in the late 1980s. flash/ee memory takes the flexible in-circuit reprogrammable features of eeprom and combines them with the space efficient/density features of eprom (see figure 14). because flash/ee technology is based on a single transistor cell architecture, a flash memory array, like eprom, can be imple- mented to achieve the space efficiencies or memory densities required by a given design. like eeprom, flash memory can be programmed in-system at a byte level, although it must first be erased in page blocks. thus, flash memory is often and more correctly referred to as flash/e e memory. flash/ee memory technology space efficient/ density in-circuit reprogrammable eprom technology eeprom technology figure 14. flash memory development overall, flash/ee memory represents a step closer to the ideal memory device that includes nonvolatility, in-circuit programma- bility, high density, and low cost. incorporated in the ADUC812, flash/ee memory technology allows the user to update program code space in-circuit without replacing one-time programmable (otp) devices at remote operating nodes. flash/ee memory and the ADUC812 the ADUC812 provides two arrays of flash/ee memory for user applications. 8k bytes of flash/ee program space are provided on-chip to facilitate code execution without any external discrete rom device requirements. the program memory can be pro- grammed using conventional third party memory programm ers. this array can also be programmed in-circuit, using the serial download mode provided. a 640 byte flash/ee data memory space is also provided on-chip as a general-purpose nonvolatile scratchpad area. user access to this area is via a group of six sfrs. ADUC812 flash/ee memory reliability the flash/ee program and data memory arrays on the ADUC812 are fully qualified for two key flash/ee memory characteristics: flash/ee memory cycling endurance and flash/ee memory data retention. endurance quantifies the ability of the flash/ee memory to be cycled through many program, re ad, and erase cycles. in real terms, a single endurance cycle is composed of four indepen dent sequential events: a. initial page erase sequence b. read/verify sequence c. byte program sequence d. second read/verify sequence in reliability qualification, ever y byte in t he progr am and data flash/ee memory is cycled from 00h to ffh until the f irst fail is recorded, signifying the endurance limit of the on- chip flash/ee memory. as indicated in the specification tables, the ADUC812 flash/ee memory endurance qualification has been carried out in accor- dance with jedec specification a117 over the industrial temperature ranges of ?0 c, +25 c, and +85 c. the results allow the specification of a minimum endurance figure over supply and temperature of 10,000 cycles, with an endur ance figure of 50,000 cycles being typical of operation at 25 c. retention quantifies the ability of the flash/ee memory to retain its programmed data over time. again, the ADUC812 has been qualified in accordance with the formal jedec retention lifetime specification (a117) at a specific junction temperature (t j = 55 c). as part of this qualification procedure, the flash/ee memory is cycled to its specified endurance limit described above, before data retention is characterized. this means that the flash/ee memory is guaranteed to retain its data for its full specified retention lifetime every time the flash/ee memory is reprogrammed.
rev. d ADUC812 ?9 using the flash/ee program memory t his 8k byte flash/ee program memory array is mapped i nto the lower 8k bytes of the 64k bytes program space address- a ble by the ADUC812 and will be used to hold user code in typical applications. the program memory array can be programmed in one of two modes: serial downloading (in-circuit programming) as part of its embedded download/debug kernel, the ADUC812 facilitates serial c ode download via the standard uart serial port. serial down load mode is automatically entered on power-up if the external pin psen is pulled low through an external resistor as shown in figure 15. once in this mode, the user can download code to the p rogram memory array while the device is sited in its target application hardware. a pc serial download executable is pro vided as part of the ADUC812 quickstart development system. the serial download protocol is detailed in a microconverter applications note uc004, available from the adi microconverter website at www.analog.com/micronverter. 1k psen ADUC812 pull psen low during reset to configure the ADUC812 for serial download mode figure 15. flash/ee memory serial download mode programming parallel programming the parallel programming mode is fully compatible with conventional third party flash or eeprom device programmers. in this mode, ports p0, p1, and p2 operate as the external data and address bus interface, ale operates as the write enable strobe, and port p3 is used as a general configuration port that configures the device for various program and erase operations during parallel programming. the high voltage (12 v) supply required for flash programming is generated using on-chip charge pumps to supply the high voltage program lines. the complete parallel programming specification is available on the microconverter homepage at www.analog.com/microconverter. u sing the flash/ee data memory the user flash/ee data memory array consists of 640 bytes that are configured into 160 (page 00h to page 9fh) 4-byte pages, as shown in figure 16. 9fh byte 1 byte 2 byte 3 byte 4 00h byte 1 byte 2 byte 3 byte 4 figure 16. user flash/ee memory configuration as with other ADUC812 user peripheral circuits, the interface to this memory space is via a group of registers mapped in the sfr space. a group of four data registers (edata14) is used to hold the 4-byte page being accessed. eadrl is used to hold the 8-bit address of the page being accessed. finally, econ is an 8-bit control register that may be written with one of five flash/ee memory access commands to trigger various read, write, erase, and verify functions. these register can be summarized as follows: econ: sfr address b9h function controls access to 640 bytes flash/ee data space. default 00h eadrl: sfr address c6h function holds the flash/ee data page address. 0h through 9fh default 00h edata1?: sfr address bch to bfh, respectively function holds the flash/ee data memory page write or page read data bytes. default edata1? ? 00h a block diagram of the sfr registered interface to the data flash/ee memory array is shown in figure 17. 9fh byte 1 byte 2 byte 3 byte 4 00h edata1 (byte 1) edata2 (byte 2) edata3 (byte 3) edata4 (byte 4) eadrl econ command interpreter logic econ byte 1 byte 2 byte 3 byte 4 function: holds the 8-bit page address pointer function: holds command word function: holds the 4-byte page word function: interprets the flash command word figure 17. user flash/ee memory control and configuration
rev. d ADUC812 ?0 econ?lash/ee memory control sfr this sfr acts as a command interpreter and may be written with one of five command modes to enable various read, pro- gram, and erase cycles as detailed in table vii. table vii. econ?lash/ee memory control register command modes command byte command mode 01h read command re sults in four bytes being read into edata1? from memory page address contained in eadrl. 02h program command re sults in four bytes (edata1?) b eing written to mem ory page address in eadrl. this write command assumes the desig nated ?rite?page has been pre-erased. 03h reserved for internal use 03h should not be written to the econ sfr. 04h verify command allows the user to verify if data in edata1? is contained in page address designated by eadrl. a subsequent read of the econ sfr will result in a zero being read if the verification is valid; a nonzero value will be read to indicate an invalid verification. 05h erase command results in an erase of the 4-byte page designated in eadrl. 06h erase-all command results in erase of the full flash/ee data memory 160-page (640 bytes) array. 07h to ffh reserved commands commands reserved for future use. flash/ee memory timing the typical program/erase times for the flash/ee data memory are: erase full array (640 bytes) 20 ms erase single page (4 bytes) 20 ms program page (4 bytes) 250 m s read page (4 bytes) within single instruction cycle flash/ee erase and program timing is derived from the master clock. when using a master clock frequency of 11.0592 mhz, it is not necessary to write to the etim registers at all. however, whe n operating at other master clock frequencies (f clk ), you must change the values of etim1 and etim2 to avoid degrad- ing data f lash/ee endurance and retention. etim1 and etim2 form a 16-bit word, etim2 being the high byte and etim1 the low byte. the value of this 16-bit word must be set as follows to ensure optimum data flash/ee endurance and retention. etim2 , etim1 = 100 m s f clk etim3 should always remain at its default value of 201 dec/c9 hex. using the flash/ee memory interface as with all flash/ee memory architectures, the array can be pro- grammed in system at a byte level, although it must be erased first, the erasure being performed in page blocks (4-byte pages in this case). a typical access to the flash/ee array will involve setting up the page address to be accessed in the eadrl sfr, configuring the edata1? with data to be programmed to the array (the edata sfrs will not be written for read accesses), and finally writing the econ command word that initiates one of the six modes shown in table vii. it should be noted that a given mode of operation is initiated as soon as the command word is written to the econ sfr. the core mi crocontroller operation on the ADUC812 is idled until the requested program/read or erase mode is completed. in practice, this means that even though the flash/ee memory mode of operation is typically initiated with a two-machine cycle mov instruction (to write to the econ sfr), the next instruction will not be executed until the flash/ee operation is complete (250 m s or 20 ms later). this means that the core will not respond to interrupt requests until the flash/ee operation is complete, although the core peripheral functions like counter/timers will continue to count and time as configured throughout this pseudo- idle period. erase-all although the 640-byte user flash/ee array is shipped from the factory pre-erased, i.e., byte locations set to ffh, it is nonetheless good programming practice to include an erase-all routine as part of any configuration/setup code running on the ADUC812. an erase-all command consists of writing 06h to the econ sfr, which initiates an erase of all 640 byte locations in the flash/ee array. this command coded in 8051 assembly would appear as: mov econ, #06h ; erase all command ; 20 ms duration program a byte in general terms, a byte in the flash/ee array can only be pro- grammed if it has previously been erased. to be more specific, a byte can only be programmed if it already holds the value ffh. because of the flash/ee architecture, this erasure must happen at a page level; therefore, a minimum of four bytes (1 page) will be erased when an erase command is initiated. a mo re specific example of the program-byte process is shown b elow. in this example, the user writes f3h into the second byte on page 03h of the flash/ee data memory space while preserving the o ther three bytes already in this page. as the user is only required to modify one of the page bytes, the full page must be first read so that this page can then be erased without the existing data being lost. this example, coded in 8051 assembly, would appear as: mov eadrl, #03h ; set page address pointer mov econ, #01h ; read page mov edata2, #0f3h ; write new byte mov econ, #05h ; erase page mov econ, #02h ; write page (program flash/ee)
rev. d ADUC812 ?1 user interface to other on-chip ADUC812 peripherals the following section gives a brief overview of the various peripherals also available on-chip. a summary of the sfrs used to control and configure these peripherals is also given. dac the ADUC812 incorporates two 12-bit voltage output dacs on-chip. each has a rail-to-rail voltage output buffer capable of driving 10 k w /100 pf. each has two selectable ranges, 0 v to v ref (the internal band gap 2.5 v reference) and 0 v to av dd . each can operate in 12-bit or 8-bit mode. both dacs share a control register, daccon, and four data registers, dac1h/l, dac0h/l. it should be noted that in 12-bit asynchronous mode, the dac voltage output will be updated as soon as the dacl data sfr has been written; therefore, the dac data registers should be updated as dach first, followed by dacl. e d o m1 g n r0 g n r1 r l c0 r l cc n y s1 d p0 d p table viii. daccon sfr bit designations bit name description 7 mode the dac mode bit sets the overriding operating mode for both dacs. set to ??= 8-bit mode (write eight bits to dacxl sfr). set to ??= 12-bit mode. 6 rng1 dac1 range select bit. set to ??= dac1 range 0? dd . set to ??= dac1 range 0? ref . 5 rng0 dac0 range select bit. set to ??= dac0 range 0? dd . set to ??= dac0 range 0? ref . 4 clr1 dac1 clear bit. set to ??= dac1 output forced to 0 v. set to ??= dac1 output normal. 3 clr0 dac0 clear bit. set to ??= dac1 output forced to 0 v. set to ??= dac1 output normal. 2 sync dac0/1 update synchronization bit. when set to ??the dac outputs update as soon as dacxl sfrs are written. the user can simultaneously update both dacs by first updating the dacxl/h sfrs while sync is ?.?both dacs will then update simultaneously when the sync bit is set to ?. 1 pd1 dac1 power-down bit. set to ??= power-on dac1. set to ??= power-off dac1. 0 pd0 dac0 power-down bit. set to ??= power-on dac0. set to ??= power-off dac0. dacxh/l dac data registers function dac data registers, written by user to update the dac output. sfr address dac0l (dac0 data low byte) ? f9h; dac1l (dac1 data low byte) ? fbh dac0h (dac0 data high byte) ? fah; dac1h(dac1 data high byte) ? fch power-on default value 00h ? all four registers bit addressable no ? all four registers the 12-bit dac data should be written into dacxh/l, right-justified such that dacl contains the lower eight bits, and the lower nibble of dach contains the upper four bits. dac control daccon register sfr address fdh power-on default value 04h bit addressable no
rev. d ADUC812 ?2 using the dac the on-chip dac architecture consists of a resistor string dac followed by an output buffer amplifier, the functional equivalent of which is illustrated in figure 18. details of the actual dac architecture can be found in u.s. patent nu mber 5969657 (www.uspto.gov). features of this architecture include inherent guaranteed monotonicity and excellent differential linearity. ADUC812 av dd v ref r r r output buffer 8 r r high-z disable (from mcu) figure 18. resistor string dac functional equivalent as illustrated in figure 18, the reference source for each dac is user selectable in software. it can be either av dd or v ref. in 0- to-av dd mode, the dac output transfer function spans from 0 v to the voltage at the av dd pin. in 0-to-v ref mode, the dac output transfer function spans from 0 v to the internal v ref, or if an external reference is applied, the voltage at the v ref pin. the dac output buffer amplifier features a true rail-to- rail output stage implementation. this means that unloaded, each output is capable of swinging to w ithin less than 100 mv of both av dd and ground. moreover, the dac? linearity specifi cation ( when driving a 10 k w resistive load to ground) is guaranteed through the full transfer function except codes 0 to 48, and, in 0- to-av dd mode only, codes 3995 to 4095. linearity degrada tion near ground and v dd is caused by saturation of the output amplifier, and a general representation of its effects (neglecting offset and gain error) is illustrated in figure 19. the dotted line in figure 19 indicates the ideal transfer function, and the solid line represents what the transfer function might look like with e ndpoint nonlinearities due to saturation of the output amplifier. note that figure 19 represents a transfer function in 0-to-v dd m ode only. in 0-to-v ref mode (with v ref < v dd ) the lower nonlinearity would be similar, but the upper portion of the transfer function would follow the ?deal?line right to the end (v ref in this case, not v dd ), showing no signs of endpoint linearity errors. v dd fff hex 000 hex v dd ?50mv v dd ?100mv 100mv 50mv 0mv figure 19. endpoint nonlinearities due to amplifier saturation the endpoint nonlinearities conceptually illustrated in figure 19 get worse as a function of output loading. most of the ADUC812? data sheet specifications assume a 10 k w resistive load to ground at the dac output. as the output is forced to source or sink more current, the nonlinear regions at the top or bottom (respectively) of figure 19 become larger. with larger current demands, this can significantly limit output voltage swing. figure 20 and figure 21 illustrate this behavior. it should be noted that the upper trace in each of these figures is only valid for an output range selection of 0-to-av dd . in 0-to-v ref mode, dac loading will not cause high-side voltage drops as long as the r eference voltage remains below the upper trace in the corre spond- ing figure. for example, if av dd = 3 v and v ref = 2.5 v, the high-side voltage will not be affected by loads less than 5 ma. but somewhere around 7 ma the upper curve in figure 21 drops below 2.5 v (v ref ), indicating that at these higher currents the output will not be capable of reaching v ref . source/sink current ?ma 5 0510 15 output voltage ?v 4 3 2 1 0 dac loaded with 0fff hex dac loaded with 0000 hex figure 20. source and sink current capability with v ref = v dd = 5 v
rev. d ADUC812 ?3 source/sink current ?ma 3 0510 15 output voltage ?v 2 1 0 figure 21. source and sink current capability with v ref = v dd = 3 v to drive significant loads with the dac outputs, external buf f ering may be required, as illustrated in figure 22. 9 ADUC812 10 figure 22. buffering the dac outputs the dac output buffer also features a high impedance disable function. in the chip? default power-on state, both dacs are disabled, and their outputs are in a high impedance state (or ?hree-state? where they remain inactive until enabled in software. this means that if a zero output is desired during power-up or power-down transient conditions, then a pull-down resistor must be added to each dac output. assuming this resistor is in place, the dac outputs will remain at ground potential whenever the dac is disabled. however, each dac output will still spike briefly when power is first applied to the chip, and again when each dac is first enabled in software. typical scope shots of these spikes are given in figure 23 and figure 24, respectively. 200 s/div av dd ?2v/div dac out ?500mv/div figure 23. dac output spike at chip power-up s/div, 1v/div 5 figure 24. dac output spike at dac enable
rev. d ADUC812 ?4 watchdog timer the purpose of the watchdog timer is to generate a device reset within a reasonable amount of time if the ADUC812 enters an erroneous state, possibly due to a programming error. the watch- dog function can be disabled by clearing the wde (watchdog enable) bit in the watchdog control (wdcon) sfr. when enabled, the watchdog circuit will generate a system reset if the user program fails to set the watchdog timer refresh bits (wdr1, wdr2) within a predetermined amount of time (see pre2? bits in wdcon). the watchdog timer itself is a 16-bit counter. the watchdog timeout interval can be adjusted via the pre2? bits in wdcon. full control and status of the watchdog timer function can be controlled via the watchdog timer control sfr (wdcon). 2 e r p1 e r p0 e r p1 r d w2 r d ws d we d w table ix. wdcon sfr bit designations bit name description 7 pre2 watchdog timer prescale bits. 6 pre1 5 pre0 pre2 pre1 pre0 timeout period (ms) 000 16 001 32 010 64 011 128 100 256 101 512 110 1024 111 2048 4 not used. 3 wdr1 watchdog timer refresh bits. set sequentially to refresh the watchdog timer. 2 wdr2 1 wds watchdog status bit. set by the watchdog controller to indicate that a watchdog timeout has occurred. cleared by writing a ??or by an external hardware reset. it is not cleared by a watchdog reset. 0 wde watchdog enable bit. set by user to enable the watchdog and clear its counters. watchdog timer wdcon control register sfr address c0h power-on default value 00h bit addressable yes example to set up the watchdog timer for a timeout period of 2048 ms, the following code would be used: mov wdcon,#0e0h ;2.048 second ;timeout period setb wde ;enable watchdog timer to prevent the watchdog timer from timing out, the timer refresh bits need to be set before 2.048 seconds has elapsed. setb wdr1 ;refresh watchdog timer.. setb wdr2 ; ..bits must be set in this ;order power supply monitor as its name suggests, the power supply monitor, once enabled, monitors both supplies (av dd and dv dd ) on the ADUC812. it will indicate when either power supply drops below one of five user selectable voltage trip points from 2.63 v to 4.63 v. for correct operation of the power supply monitor function, av dd must be equal to or greater than 2.7 v. the power supply monitor function is controlled via the psmcon sfr. if enabled via the ie2 sfr, the power supply monitor will interrupt the core using the psmi bit in the psmcon sfr. this bit will not be cleared until the failing power supply has returned above the trip point for at least 256 ms. t his ensures that the power supply has fully settled before the bit is cleared. this mon ito r function allows the user to save working registers to avoid possible data loss due to the low supply condition, and also en sures that nor mal code execution will not resume until a safe supply level has been well established. the supply monitor is also protected against spurious glitches triggering the interrupt circuit.
rev. d ADUC812 ?5 power supply monitor psmcon control register sfr address dfh power-on default value dch bit addressable no ? m ci m s p2 p t1 p t0 p tf s pn e m s p table x. psmcon sfr bit designations bit name description 7 not used. 6 cmp av dd and dv dd comparator bit. this is a read-only bit and directly reflects the state of the av dd and dv dd comparators. read ??indicates that both the av dd and dv dd supplies are above their selected trip points. read ??indicates that either the av dd or dv dd supply is below its selected trip point. 5 psmi power supply monitor interrupt bit. this bit will be set high by the microconverter if cmp is low, indicating low analog or digital supply. the psmi bit can be used to interrupt the processor. once cmpd and/or cmp return (and remain) high, a 256 ms counter is started. when this counter times out, the psmi interrupt is cleared. psmi can also be written by the user. however, if either comparator output is low, it is not possible for the user to clear psmi. 4 tp2 v dd trip point selection bits. 3 tp1 2 tp0 these bits select the av dd and dv dd trip point voltage as follows: tp2 tp1 tp0 selected dv dd trip point (v) 0004.63 0014.37 0103.08 0112.93 1002.63 1 psf av dd /dv dd fault indicator. read ??indicates that the av dd supply caused the fault condition. read ??indicates that the dv dd supply caused the fault condition. 0 psmen power supply monitor enable bit. set to ??by the user to enable the power supply monitor circuit. cleared to ??by the user to disable the power supply monitor circuit. example to configure the psm for a trip point of 4.37 v, the following code would be used: mov psmcon,#005h ;enable psm with ;4.37v threshold setb ea ;enable interrupts mov ie2,#002h ;enable psm ;interrupt if the supply voltage falls below this level, the pc would vector to the isr. org 0043h ;psm isr check:mov a,psmcon ;psmcon.5 is the ;psm interrupt ;bit.. jb acc.5,check ;..it is cleared ;only when vdd ;has remained ;above the trip ;point for 256ms ;or more. reti ; return only when "all's well" serial peripheral interface the ADUC812 integrates a complete hardware serial peripheral interface (spi) on-chip. spi is an industry-standard synchronous serial interface that allows eight bits of data to be synchronously transmitted and received simultaneously, i.e., full duplex. it should be noted that the spi pins are shared with the i 2 c interface, and therefore the user can only enable one or the other interface at any given time (see spe in table xi ). the spi port can be con- figured for master or slave operation and typically consists of four pins, namely: miso (master in, slave out data i/o pin) the miso (master in, slave out) pin is configured as an input line in master mode a nd an output line in slave mode. the miso line on the master (data in) should be connected to the miso line in the slave device (data out). the data is transferred as byte wide (8-bit) serial data, msb first.
rev. d ADUC812 ?6 mosi (master out, slave in pin) the mosi (master out, slave in) pin is configured as an output line in master mode and an input line in slave mode. the mosi line on the master (data out) should be connected to the mosi line in the slave device (data in). the data is transferred as byte wide (8-bit) serial data, msb first. sclock (serial clock i/o pin) the master serial clock (sclock) is used to synchronize the data being transmitted and received through the mosi and miso data lines. a single data bit is transmitted and received in each sclock period. therefore, a byte is transmitted/received after eight sclock periods. the sclock pin is configured as an output in master mode and as an input in slave mode. in master mode, the bit rate, polarity, and phase of the clock are con trolled by the cpol, cpha, spr0, and spr1 bits in the spicon sfr (see table xi). in slave mode, the spicon register will have to be configured with the phase and polarity (cpha and cpol) of the expected input clock. in both master and slave modes, the da ta is transmitted on one edge of the sclock signal and sampled on the other. it is important therefore that the cpha and cpol are configured the same for the master and slave devices. ss (slave select input pin) the slave select ( ss ) input pin is shared with the adc5 input. to configure this pin as a digital input, the bit must be cleared, e.g., clr p1.5. this line is active low. data is only received or transmitted in slave mode when the ss pin is low, allowing the ADUC812 to be used in single master, multislave spi configurations. if cpha = 1, then the ss input may be permanently pulled low. with cpha = 0, the ss input must be driven low before the first bit in a byte wide transmission or reception, and return high again after the last bit in that byte wide transmission or reception. in spi slave mode, the logic level on the external ss p in can be read via the spr0 bit in the spicon sfr. the follow- ing sfr registers are used to control the spi interface. spi control spicon register sfr address f8h power-on default value ooh bit addressable yes i p s il o c we p sm i p sl o p ca h p c1 r p s0 r p s table xi. spicon sfr bit designations bit name description 7 ispi spi interrupt bit. set by microconverter at the end of each spi transfer. cleared directly by user code or indirectly by reading the spidat sfr. 6 wcol write collision error bit. set by microconverter if spidat is written to while an spi transfer is in progress. cleared by user code. 5 spe spi interface enable bit. set by user to enable the spi interface. cleared by user to enable i 2 c interface. 4 spim spi master/slave mode select bit. set by user to enable master mode operation (sclock is an output). cleared by user to enable slave mode operation (sclock is an input). 3 cpol * clock polarity select bit. set by user if sclock idles high. cleared by user if sclock idles low. 2 cpha * clock phase select bit. set by user if leading sclock edge is to transmit data. cleared by user if trailing sclock edge is to transmit data. 1 spr1 spi bit rate select bits. 0 spr0 these bits select the sclock rate (bit rate) in master mode as follows: spr1 spr0 selected bit rate 00f osc /4 01f osc /8 10f osc /32 11f osc /64 in spi slave mode, i.e., spim = 0, the logic level on the external ss pin can be read via the spr0 bit. * the cpol and cpha bits should both contain the same values for master and slave devices.
rev. d ADUC812 ?7 spi interface?aster mode in master mode, the sclock pin is always an output and gener- ates a bu rst of eight clocks whenever user code writes to the spidat register. the sclock bit rate is determined by spr0 and spr1 in spicon. it should also be noted that the ss pin is not used in master mode. if the ADUC812 needs to assert the ss pin on an external slave device, a port digital output pin should be used. in master mode a byte transmission or reception is initiated by a write to spidat. eight clock periods are generated via the sclock pin and the spidat byte being transmitted via mosi. with each sclock period a data bit is also sampled via m iso . after eight clocks, the transmitted byte will have been completely transmitted and the input byte will be waiting in t he input shift register. the ispi flag will be set automatically and an interrupt w ill occur if enabled. the value in the shift register will be latched into spi dat. spi interface?lave mode in slave mode the sclock is an input. the ss pin must also be driven low externally during the byte communication. transmission is also initiated by a write to spidat. in slave mode, a data bit is transmitted via miso and a data bit is received via mosi through each input sclock period. after eight clocks, the transmitted byte will have been completely transmitted and the i nput byte will be waiting in the input shift register. the ispi flag w ill be set automatically and an interrupt will occur if enabled. t he value in the shift register will be latched into spidat only when the transmission/reception of a byte has been completed. the end of transmission occurs after the eighth clock has been received if cpha = 1, or when ss returns high if cpha = 0. spidat spi data register function the spidat sfr is written by the user to transmit data over the spi i nterface or read by user code to read data just received by the spi interface. sfr address f7h power-on default value 00h bit addressable no using the spi interface depending on the configuration of the bits in the spicon sfr shown in table xi, the ADUC812 spi interface will transmit or receive data in a number of possible modes. figure 25 shows all possible ADUC812 spi configurations and the timing relation ships and synchronization between the signals involved. also shown in this figure is the spi interrupt bit (ispi) and how it is triggered at the end of each byte wide communication. msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ? msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb ? sclock (cpol = 1) sclock (cpol = 0) ss sample input data output ispi flag sample input data output ispi flag (cpha = 1) (cpha = 0) figure 25. spi timing, all modes
rev. d ADUC812 ?8 i2cadd i 2 c address register function holds the i 2 c peripheral address for the part. it may be overwritten by the user code. application note uc001 at www.analog.com/microconverter describes the format of the i 2 c standard 7-bit address in detail. sfr address 9bh power-on default value 55h bit addressable no i2cdat i 2 c data register function the i2cdat sfr is written by the user to transmit data over the i 2 c interface or read by user code to read data just received by the i 2 c interface. user software should only access i2cdat once per interrupt cycle. sfr address 9ah power-on default value 00h bit addressable no o d me d mo c mi d mm c 2 is r c 2 ix t c 2 ii c 2 i table xii. i2ccon sfr bit designations bit name description 7 mdo i 2 c software master data output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be output on the sdata pin if the data output enable (mde) bit is set. 6 mde i 2 c software master data output enable bit (master mode only). set by the user to enable the sdata pin as an output (tx). cleared by the user to enable sdata pin as an input (rx). 5 mco i 2 c software master data output bit (master mode only). this data bit is used to implement a master i 2 c transmitter interface in software. data written to this bit will be output on the sclock pin. 4 mdi i 2 c software master data input bit (master mode only). this data bit is used to implement a master i 2 c receiver interface in software. data on the sdata pin is latched into this bit on sclock if the data output enable (mde) = 0. 3 i2cm i 2 c master/slave mode bit. set by user to enable i 2 c software master mode. cleared by user to enable i 2 c hardware slave mode. 2 i2crs i 2 c reset bit (slave mode only). set by user to reset the i 2 c interface. cleared by user for normal i 2 c operation. 1i 2ctx i 2 c direction transfer bit (slave mode only). set by the microconverter if the interface is transmitting. cleared by the microconverter if the interface is receiving. 0 i2ci i 2 c interrupt bit (slave mode only). set by the microconverter after a byte has been transmitted or received. cleared by user software. i 2 c compatible interface the ADUC812 supports a 2-wire serial interface mode that is i 2 c compatible. the i 2 c compatible interface shares its pins with the on-chip spi interface and therefore the user can only enable one or the other interface at any given time (see spe in table ix). an application note describing the operation of this interface as implemented is available from the microconverter website at www.analog.com/microconverter. this interface can be configured as a software master or hardware slave, and uses two pins in the interface. sdata serial data i/o pin sclock serial clock three sfrs are used to control the i 2 c compatible interface. these are described below: i2ccon i 2 c control register sfr address e8h power-on default value 00h bit addressable yes
rev. d ADUC812 ?9 8051 compatible on-chip peripherals this section gives a brief overview of the various secondary peripheral circuits that are also available to the user on-chip. these remaining functions are fully 8051 compatible and are controlled via standard 8051 sfr bit definitions. parallel i/o ports 0? the ADUC812 uses four input/output ports to exchange data with external devices. in addition to performing general-purpose i/o, some ports are capable of external memory operations; others are multiplexed with an alternate function for the peripheral fea tures on the device. in general, when a peripheral is enabled, that pin may not be used as a general-purpose i/o pin. port 0 is an 8-bit, open-drain, bidirectional i/o port that is directly controlled via the p0 sfr (sfr address = 80h). port 0 pins that have 1s written to them via the port 0 sfr will be configured as open-drain and will therefore float. in that state, port 0 pins can be used as high impedance inputs. an external pull-up resistor will be required on p ort 0 outputs to force a valid logic high level externally. port 0 is also the multiplexed low order address and data bus during accesses to external program or data memory. in this application, it uses strong internal pull-ups when emitting 1s. port 1 is also an 8-bit port directly controlled via the p1 sfr (sfr address = 90h). port 1 is an input only port. port 1 digital output capability is not supported on this device. port 1 pins can be configured as digital inputs or analog inputs. by (power-on) default these pins are configured as analog inputs, i.e., ? written in the corresponding port 1 register bit. to configure any of these pins as digital inputs, the user should write a ??to these port bits to configure the corresponding pin as a high impedance digital input. these pins also have various secondary functions described in table xiii. table xiii. port 1, alternate pin functions pin alternate function p1.0 t2 (timer/counter 2 external input) p1.1 t2ex (timer/counter 2 capture/reload trigger) p1.5 ss (slave select for the spi interface) port 2 is a bidirectional port with internal pull-up resistors directly controlled via the p2 sfr (sfr address = a0h). port 2 pins that have 1s written to them are pulled high by the internal pull-up resistors and, in that state, can be used as inputs. as inputs, port 2 pins being pulled externally low will source current because of the internal pull-up resistors. port 2 emits the high order ad dress bytes during fetches from external program memory, and middle and high order address bytes during accesses to the 24-bit external data memory space. por t 3 is a bidirectional port with internal pull-ups directly controlled via the p3 sfr (sfr address = b0h). port 3 pins that have 1s written to them are pulled high by the internal pull-ups and, in that state, can be used as inputs. as inputs, port 3 pins being pulled externally low will source current be cause of the internal pull-ups. port 3 pins also have various secondary functions described in table xiv. table xiv. port 3, alternate pin functions pin alternate function p3.0 rxd (uart input pin) (or serial data i/o in mode 0) p3.1 txd (uart output pin) (or serial clock output in mode 0) p3.2 int0 (external interrupt 0) p3.3 int1 (external interrupt 1) p3.4 t0 (timer/counter 0 external input) p3.5 t1 (timer/counter 1 external input) p3.6 wr (external data memory write strobe) p3.7 rd (external data memory read strobe) the alternate functions of p1.0, p1.1, p1.5, and port 3 pins can be activated only if the corresponding bit latch in the p1 a nd p3 sfrs contains a 1. otherwise, the port pin is stuck at 0. timers/counters the ADUC812 has three 16-bit timer/counters: timer 0, timer 1, and timer 2. the timer/counter hardware has been included on-chip to relieve the processor core of the overhead inherent in implementing timer/counter functionality in software. each timer/counter consists of two 8-bit registers, thx and tlx (x = 0, 1, and 2). all three can be configured to operate either as timers or event counters. in timer function, the tlx register is incremented every machine cycle. thus, think of it as counting machine cycles. since a machine cycle consists of 12 core clock periods, the maximum count rate is 1/12 of the core clock frequency. in counter function, the tlx register is incremented by a 1-to-0 transition at its corresponding external input pin, t0, t1, or t2. in this function, the external input is sampled during s5p2 of every machine cycle. when the samples show a high in one cycle and a low in the next cycle, the count is incremented. the new count value appears in the register during s3p1 of the cycle following the one in which the transition was detected. since it takes two machine cycles (24 core clock periods) to recognize a 1-to-0 transition, the maximum count rate is 1/24 of the core clock frequency. there are no restrictions on the duty cycle of the external input signal, but to ensure that a given level is sampled at least once before it changes, it must be held for a minimum of one full machine cycle.
rev. d ADUC812 ?0 table xv. tmod sfr bit designations bit name description 7 gate timer 1 gating control. set by software to enable timer/counter 1 only while int1 pin is high and tr1 control bit is set. cleared by software to enable timer 1 whenever tr1 control bit is set. 6 c/t timer 1 timer or counter select bit. set by software to select counter operation (input from t1 pin). cleared by software to select timer operation (input from internal system clock). 5m 1t imer 1 mode select bit 1 (used with m0 bit). 4m 0t imer 1 mode select bit 0. m1 m0 00 th1 operates as an 8-bit timer/counter. tl1 serves as 5-bit prescaler. 01 16-bit timer/counter. th1 and tl1 are cascaded; there is no prescaler. 10 8-bit autoreload timer/counter. th1 holds a value that is to be reloaded into tl1 each time it overflows. 11 timer/counter 1 stopped. 3 gate timer 0 gating control. set by software to enable timer/counter 0 only while int0 pin is high and tr0 control bit is set. cleared by software to enable timer 0 whenever tr0 control bit is set. 2 c/t timer 0 timer or counter select bit. set by software to select counter operation (input from t0 pin). cleared by software to select timer operation (input from internal system clock). 1m 1t imer 0 mode select bit 1. 0m 0t imer 0 mode select bit 0. m1 m0 00 th0 operates as an 8-bit timer/counter. tl0 serves as 5-bit prescaler. 01 16-bit timer/counter. th0 and tl0 are cascaded; there is no prescaler. 10 8-bit autoreload timer/counter. th0 holds a value that is to be reloaded into tl0 each time it overflows. 11 tl0 is an 8-bit timer/counter controlled by the standard timer 0 control bits. th0 is an 8-bit timer only, controlled by timer 1 control bits. user configuration and control of all timer operating modes is achieved via three sfrs: tmod, tcon control and configuration for timers 0 and 1. t2con control and configuration for timer 2. timer/counter 0 and tmod 1 mode register sfr address 89h power-on default value 00h bit addressable no e t a gt / c1 m0 me t a gt / c1 m0 m
rev. d ADUC812 ?1 * these bits are not used in the control of timer/counter 0 and 1, but are used instead in the control and monitoring of the exte rnal int0 and int1 interrupt pins. table xvi. tcon sfr bit designations bit name description 7 tf1 timer 1 overflow flag. set by hardware on a timer/counter 1 overflow. cleared by hardware when the program counter (pc) vectors to the interrupt service routine. 6 tr1 timer 1 run control bit. set by user to turn on timer/counter 1. cleared by user to turn off timer/counter 1. 5 tf0 timer 0 overflow flag. set by hardware on a timer/counter 0 overflow. cleared by hardware when the pc vectors to the interrupt service routine. 4 tr0 timer 0 run control bit. set by user to turn on timer/counter 0. cleared by user to turn off timer/counter 0. 3 ie1 external interrupt 1 ( int1 ) flag. set by hardware by a falling edge or zero level being applied to external interrupt pin int1 , depending on bit it1 state. cleared by hardware when the when the pc vectors to the interrupt service routine only if the interrupt was transition-activated. if level-activated, the external requesting source controls the request flag, rather than the on-chip hardware. 2 it1 external interrupt 1 (ie1) trigger type. set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). cleared by software to specify level-sensitive detection (i.e., zero level). 1 ie0 external interrupt 0 ( int0 ) flag. set by hardware by a falling edge or zero level being applied to external interrupt pin int0 , depending on bit it0 state. cleared by hardware when the pc vectors to the interrupt service routine only if the interrupt was transition activated. if level activated, the external requesting source controls the request flag, rather than the on-chip hardware. 0 it0 external interrupt 0 (ie0) trigger type. set by software to specify edge-sensitive detection (i.e., 1-to-0 transition). cleared by software to specify level-sensitive detection (i.e., zero level). timer/counters 0 and 1 data registers each timer consists of two 8-bit registers. these can be used as independent registers or combined to be a single 16-bit register depending on the timer mode configuration. th0 and tl0 timer 0 high byte and low byte. sfr address = 8ch, 8ah, respectively. th1 and tl1 timer 1 high byte and low byte. sfr address = 8dh, 8bh, respectively. timer/counter 0 and tcon 1 control register sfr address 88h power-on default value 00h bit addressable yes 1 f t1 r t0 f t0 r t1 e i * 1 t i * 0 e i * 0 t i *
rev. d ADUC812 ?2 mode 2 (8-bit timer/counter with auto reload) mode 2 configures the timer register as an 8-bit counter (tl0) with automatic reload, as shown in figure 28. overflow from tl0 not only sets tf0, but also reloads tl0 with the contents of th0, which is preset by software. the reload leaves th0 unchanged. 12 core clk tf0 control p3.4/t0 tl0 (8 bits) interrupt c/t = 0 c/t = 1 reload th0 (8 bits) gate p3.2/int0 tr0 figure 28. timer/counter 0, mode 2 mode 3 (two 8-bit timer/counters) mode 3 has different effects on timer 0 and timer 1. timer 1 in mode 3 simply holds its count. the effect is the same as setting tr1 = 0. timer 0 in mode 3 establishes tl0 and th0 as two separate counters. this configuration is shown in figure 29. tl0 uses the timer 0 control bits: c/t, gate, tr0, int0 , and tf0. th0 is locked into a timer function (counting machine cycles) and takes over the use of tr1 and tf1 from timer 1. thus, th0 now controls the timer 1 interrupt. mode 3 is provided for applications requiring an extra 8-bit timer or counter. when timer 0 is in mode 3, timer 1 can be turned on and off by switching it out of, and into, its own mode 3, or can still be used by the serial interface as a baud rate generator . in fact, it can be used in any application not requiring an interrupt from timer 1 itself. 12 core clk tl0 (8 bits) tf0 interrupt control p3.4/t0 c/t = 0 c/t = 1 th0 (8 bits) core clk/12 tr1 core clk/12 control gate p3.2/int0 tr0 tf1 interrupt figure 29. timer/counter 0, mode 3 timer/counters 0 and 1 operating modes the following paragraphs describe the operating modes for timer/counters 0 and 1. unless otherwise noted, it should be assumed that these modes of operation are the same for timer 0 as for timer 1. mode 0 (13-bit timer/counter) mode 0 configures an 8-bit timer/counter with a divide-by-32 prescaler. figure 26 shows mode 0 operation. 12 core clk p3.4/t0 gate p3.2/int0 tr0 tf0 control tl0 (5 bits) th0 (8 bits) interrupt c/t = 0 c/t = 1 figure 26. timer/counter 0, mode 0 in this mode, the timer register is configured as a 13-bit register. as the count rolls over from all 1s to all 0s, it sets the timer overflow flag tf0. the overflow flag, tf0, can then be used to request an interrupt. the counted input is enabled to the timer when tr0 = 1 and either gate = 0 or int0 = 1. setting gate = 1 allows the timer to be controlled by external input int0 to facilitate pulsewidth measurements. tr0 is a control bit in the special function register tcon; gate is in tmod. the 13-bit register consists of all eight bits of th0 and the lower five bits of tl0. the upper three bits of tl0 are indeterminate and should be ignored. setting the run flag (tr0) does not clear the registers. mode 1 (16-bit timer/counter) mode 1 is the same as mode 0, except that the timer register is running with all 16 bits. mode 1 is shown in figure 27. 12 core clk tf0 control p3.4/t0 tl0 (8 bits) th0 (8 bits) interrupt c/t = 0 c/t = 1 gate p3.2/int0 tr0 figure 27. timer/counter 0, mode 1
rev. d ADUC812 ?3 timer/counter 2 t2con control register sfr address c8h power-on default value 00h bit addressable yes 2 f t2 f x ek l c rk l c t2 n e x e2 r t2 t n c2 p a c table xvii. t2con sfr bit designations bit name description 7 tf2 timer 2 overflow flag. set by hardware on a timer 2 overflow. tf2 will not be set when either rclk = 1 or tclk = 1. cleared by user software. 6 exf2 timer 2 external flag. set by hardware when either a capture or reload is caused by a negative transition on t2ex and exen2 = 1. cleared by user software. 5 rclk receive clock enable bit. set by user to enable the serial port to use timer 2 overflow pulses for its receive clock in serial port modes 1 and 3. cleared by user to enable timer 1 overflow to be used for the receive clock. 4 tclk transmit clock enable bit. set by user to enable the serial port to use timer 2 overflow pulses for its transmit clock in serial port modes 1 and 3. cleared by user to enable timer 1 overflow to be used for the transmit clock. 3 exen2 timer 2 external enable flag. set by user to enable a capture or reload to occur as a result of a negative transition on t2ex if timer 2 is not being used to clock the serial port. cleared by user for timer 2 to ignore events at t2ex. 2 tr2 timer 2 start/stop control bit. set by user to start timer 2. cleared by user to stop timer 2. 1 cnt2 timer 2 timer or counter function select bit. set by the user to select counter function (input from external t2 pin). cleared by the user to select timer function (input from on-chip core clock). 0 cap2 timer 2 capture/reload select bit. set by user to enable captures on negative transitions at t2ex if exen2 = 1. cleared by user to enable autoreloads with timer 2 overflows or negative transitions at t2ex when exen2 = 1. when either rclk = 1 or tclk = 1, this bit is ignored and the timer is forced to autoreload on timer 2 overflow. timer/counter 2 data registers timer/counter 2 also has two pairs of 8-bit data registers associated with it. these are used as both timer data registers and timer capture/reload registers. th2 and tl2 timer 2, data high byte and low byte. sfr address = cdh, cch, respectively. rcap2h and rcap2l timer 2, capture/reload high byte and low byte. sfr address = cbh, cah, respectively.
rev. d ADUC812 ?4 timer/counter operation modes the following paragraphs describe the operating modes for ti m er/ counter 2. the operating modes are selected by bits in the t2con sfr as shown in table xviii. table xviii. timecon sfr bit designations rclk (or) tclk cap2 tr2 mode 00 1 16-bit autoreload 01 1 16-bit capture 1x 1b aud rate xx0 off 16-bit autoreload mode in autoreload mode, there are two options, which are selected by bit exen2 in t2con. if exen2 = 0, then when timer 2 rolls over, it not only sets tf2 but also causes the timer 2 registers to reload with the 16-bit value in registers rcap2l and rcap2h, which are preset by software. if exen2 = 1 then timer 2 still performs the above, but with the added feature that a 1-to-0 transition at external input t2ex will also trigger the 16-bit reload and set exf2. the autoreload mode is illustrated in figure 30. 16-bit capture mode in the capture mode, there are again two options, which are selected by bit exen2 in t2con. if exen2 = 0, then timer 2 is a 16-bit timer or counter that, upon overflowing, sets bit tf2, the timer 2 overflow bit, that can be used to generate an inter- rupt. if exen2 = 1, then timer 2 still performs the above, but a l-to-0 transition on external input t2ex causes the current value in the timer 2 registers, tl2 and th2, to be captured into registers rcap2l and rcap2h, respectively. in addition, the transition at t2ex causes bit exf2 in t2con to be set, and exf2, like tf2, can generate an interrupt. the capture mode is illustrated in figure 31. the baud rate generator mode is selected by rclk = 1 and/or tclk = 1. in either case, if timer 2 is being used to generate the baud rate, the tf2 interrupt flag will not occur. therefore timer 2 inter- rupts will not occur, so they do not have to be disabled. in this mode however, the exf2 flag can still cause interrupts and this can be used as a third external interrupt. baud rate generation will be described as part of the uart serial port operation in the following pages. core clk 12 t2 pin c/t2 = 0 c/t2 = 1 tr2 control tl2 (8 bits) th2 (8 bits) reload tf2 exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h figure 30. timer/counter 2, 16-bit autoreload mode tf2 core clk 12 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) capture exf2 timer interrupt exen2 control transition detector t2ex pin rcap2l rcap2h c/t2 = 0 c/t2 = 1 figure 31. timer/counter 2, 16-bit capture mode
rev. d ADUC812 ?5 uart serial interface t he serial port is full-duplex, meaning it can transmit and receive si multaneously. it is also receive-buffered, meaning it can begin receiving a second byte before a previously received byte has been read from the receive register. however, if the first byte still has not been read by the time reception of the second byte is com- plete, the first byte will be lost. the physical in terface to the serial data network is via pins rxd(p3.0) and txd(p3.1) while the sfr interface to the uart is comprised of sbuf and scon, as described below. sbuf the serial port receive and transmit registers are both accessed through the sbuf sfr (sfr address = 99h). w riting to sbuf loads the transmit register and reading sbuf accesses a physically separate receive register. uart serial port scon control register sfr address 98h power-on default value 00h bit addressable yes 0 m s1 m s2 m sn e r8 b t8 b ri ti r table xix. scon sfr bit designations bit name description 7 sm0 uart serial mode select bits. 6 sm1 these bits select the serial port operating mode as follows: sm0 sm1 selected operating mode 00 mode 0: shift register, fixed baud rate (core_clk/2) 01 mode 1: 8-bit uart, variable baud rate 10 mode 2: 9-bit uart, fixed baud rate (core_clk/64) or (core_clk/32) 11 mode 3: 9-bit uart, variable baud rate 5 sm2 multiprocessor communication enable bit. enables multiprocessor communication in modes 2 and 3. in mode 0, sm2 should be cleared. in mode 1, if sm2 is set, ri will not be activated if a valid stop bit was not received. if sm2 is cleared, ri will be set as soon as the byte of data has been received. in modes 2 or 3, if sm2 is set, ri will not be activated if the received ninth data bit in rb8 is 0. if sm2 is cleared, ri will be set as soon as the byte of data has been received. 4 ren serial port receive enable bit. set by user software to enable serial port reception. cleared by user software to disable serial port reception. 3t b8 serial port transmit (bit 9). the data loaded into tb8 will be the ninth data bit that will be transmitted in modes 2 and 3. 2 rb8 serial port receiver bit 9. the ninth data bit received in modes 2 and 3 is latched into rb8. for mode 1, the stop bit is latched into rb8. 1t i serial port transmit interrupt flag. set by hardware at the end of the eighth bit in mode 0, or at the beginning of the stop bit in modes 1, 2, and 3. ti must be cleared by user software. 0r i serial port receive interrupt flag. set by hardware at the end of the eighth bit in mode 0, or halfway through the stop bit in modes 1, 2, and 3. ri must be cleared by software.
rev. d ADUC812 ?6 mode 0 (8-bit shift register mode) mode 0 is selected by clearing both the sm0 and sm1 bits in the s fr scon. serial data enters and exits through rxd. txd outputs the shift clock. eight data bits are transmitted or received. transmission is initiated by any instruction that writes to s buf. the data is shifted out of the rxd line. the eight bits are transmitted with the least significant bit (lsb) first, as shown in figure 32. core clk ale rxd (data out) txd (shift clock) data bi t 0 dat a bi t 1 data bi t 6 data bi t 7 s6 s5 s4 s3 s2 s1 s6 s5 s4 s4 s3 s2 s1 s6 s5 s4 s3 s2 s1 ma chine cycle 8 ma chine cycle 7 ma chine cycle 2 ma chine cycle 1 figure 32. uart serial port transmission, mode 0 reception is initiated when the receive enable bit (ren) is 1 and the receive interrupt bit (ri) is 0. when ri is cleared, the data is clocked into the rxd line and the clock pulses are output from the txd line. mode 1 (8-bit uart, variable baud rate) mode 1 is selected by clearing sm0 and setting sm1. each data byte (lsb first) is preceded by a start bit (0) and followed by a stop bit (1). therefore 10 bits are transmitted on txd or received on rxd. the baud rate is set by the timer 1 or timer 2 overflow rate, or a combination of the two (one for transmission and the other for reception). transmission is initiated by writing to sbuf. the ?rite to sbuf signal also loads a 1 (stop bit) into the ninth bit position of the transmit shift register. the data is output bit by bit until the stop bit appears on txd and the transmit interrupt flag (ti) is auto- matically set, as shown in figure 33. txd ti (sco n.1) start bit d0 d1 d2 d3 d4 d5 d6 d7 stop bit set interrupt i.e., ready for more data figure 33. uart serial port transmission, mode 0 reception is initiated when a 1-to-0 transition is detected on rx d. assuming a valid start bit was detected, character reception continues. the start bit is skipped and the eight data bits are clocked into the serial port shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf. the ninth bit (stop bit) is clocked into rb8 in scon. the receiver interrupt flag (ri) is set. this will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0 or sm2 = 1 and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 2 (9-bit uart with fixed baud rate) mode 2 is selected by setting sm0 and clearing sm1. in this mode, the uart operates in 9-bit mode with a fixed baud rate. the baud rate is fixed at core_clk/64 by default, although by setting the smod bit in pcon, the frequency can be doubled to core_clk/32. eleven bits are transmitted or received, a start bit (0), eight data bits, a programmable ninth bit, and a stop bit (1). the ninth bit is most often used as a parity bit, although it can be used for anything, including a ninth data bit if required. to transmit, the eight data bits must be written into sbuf. the ninth bit must be written to tb8 in scon. when transmission is initiated, the eight data bits (from sbuf) are loaded onto the transmit shift register (lsb first). the contents of tb8 are loaded into the ninth bit position of the transmit shift register. the trans- mission will start at the next valid baud rate clock. the ti flag is set as soon as the stop bit appears on txd. reception for mode 2 is similar to that of mode 1. the eight data bytes are input at rxd (lsb first) and loaded onto the receive shift register. when all eight bits have been clocked in, the following events occur: the eight bits in the receive shift register are latched into sbuf. the ninth data bit is latched into rb8 in scon. the receiver interrupt flag (ri) is set. this will be the case if, and only if, the following conditions are met at the time the final shift pulse is generated: ri = 0, and either sm2 = 0, or sm2 = 1 and the received stop bit = 1. if either of these conditions is not met, the received frame is irretrievably lost, and ri is not set. mode 3 (9-bit uart with variable baud rate) mode 3 is selected by setting both sm0 and sm1. in this mode the 8051 uart serial port operates in 9-bit mode with a variable baud rate determined by either timer 1 or timer 2. the opera- tion of the 9-bit uart is the same as for mode 2, but the baud rate can be varied as for mode 1. in all four modes, transmission is initiated by any instruction that uses sbuf as a destination register. reception is initiated in mode 0 by the condition ri = 0 and ren = 1. reception is initiated in the other modes by the incoming start bit if ren = 1. uart serial port baud rate generation mode 0 baud rate generation the baud rate in mode 0 is fixed: mode baud rate core clock frequency 012 = () mode 2 baud rate generation the baud rate in mode 2 depends on the value of the smod bit in the pcon sfr. if smod = 0, the baud rate is 1/64 of the core clock. if smod = 1, the baud rate is 1/32 of the core clock: mode baud rate core clock frequency smod 2264 = () () mode 1 and 3 baud rate generation the baud rates in modes 1 and 3 are determined by the overflow rate in timer 1 or timer 2, or both (one for transmit and the other for receive).
rev. d ADUC812 ?7 timer 1 generated baud rates when timer 1 is used as the baud rate generator, the baud rates in modes 1 and 3 are determined by the timer 1 overflow rate and the value of smod as follows: the timer 1 interrupt should be disabled in this application. the timer itself can be configured for either timer or counter operati on, and in any of its three running modes. in the most typical application, it is configured for timer operation in the autoreload mode (high nibble of tmod = 0010 binary). in that case, the baud rate is given by the formula: table xx shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 mhz an d 12 mhz. generally speaking, a 5% error is tolerable using asynchronous (start/stop) communications. table xx. commonly used baud rates, timer 1 ideal core smod th1-reload actual % baud clk value value baud error 9600 12 1 ? (f9h) 8929 7 19200 11.0592 1 ? (fdh) 19200 0 9600 11.0592 0 ? (fdh) 9600 0 2400 11.0592 0 ?2 (f4h) 2400 0 timer 2 generated baud rates baud rates can also be generated using timer 2. using timer 2 is similar to using timer 1 in that the timer must overflow 16 times before a bit is transmitted/received. because timer 2 has a 16-bit autoreload mode, a wider range of baud rates is possible using timer 2. modes and baud rate timer overflow rate 13 = () () 116 2 therefore, when timer 2 is used to generate baud rates, the timer increments every two clock cycles and not every core machine cycle as before. therefore, it increments six times faster than timer 1, and baud rates six times faster are possible. because timer 2 has 16-bit autoreload capability, very low baud rates are still possible. timer 2 is selected as the baud rate generator by setting the tclk and/or rclk in t2con. the baud rates for transmit and receive can be simultaneously different. setting rclk and/or tclk puts timer 2 into its baud rate generator mode as shown in figure 34. in this case, the baud rate is given by the formula: modes and baud rate core clk rcap h rcap l 13 = () - () [] () 32 65536 2 2 , table xxi shows some commonly used baud rates and how they might be calculated from a core clock frequency of 11.0592 mhz and 12 mhz. table xxi. commonly used baud rates, timer 2 ideal core rcap2h rcap2l actual % baud clk value value baud error 19200 12 ? (ffh) ?0 (ech) 19661 2.4 9600 12 ? (ffh) ?1 (d7h) 9591 0.1 2400 12 ? (ffh) ?64 (5ch) 2398 0.1 1200 12 ? (feh) ?2 (b8h) 1199 0.1 19200 11.0592 ? (ffh) ?8 (eeh) 19200 0 9600 11.0592 ? (ffh) ?6 (dch) 9600 0 2400 11.0592 ? (ffh) ?44 (70h) 2400 0 1200 11.0592 ? (ffh) ?2 (e0h) 1200 0 core clk 2 t2 pin tr2 control tl2 (8 bits) th2 (8 bits) reload exen2 control t2ex pin rcap2l rcap2h note: oscillator frequency is divided by 2, not 12. timer 2 overflow 2 16 16 rclk tclk rx clock tx clock 0 0 1 1 1 0 smod timer 1 overflow transition detector exf 2 timer 2 interrupt note: availability of additional external interrupt c/t2 = 0 c/t2 = 1 figure 34. timer 2, uart baud rates modes and baud rate timer overflow rate smod 13 = () () 232 1 modes and baud rate core clock th smod 13 = () - [] () () 232 12 256 1
rev. d ADUC812 ?8 interrupt system the ADUC812 provides a total of nine interrupt sources with two priority levels. the control and configuration of the interrupt system is carried out through three interrupt related sfrs. ie interrupt enable register ip interrupt priority register ie2 secondary interrupt enable register interrupt enable ie register sfr address a8h power-on default value 00h bit addressable yes a ec d a e2 t es e1 t e1 x e0 t e0 x e table xxii. ie sfr bit designations bit name description 7e aw ritten by user to enable ??or disable ??all interrupt sources. 6 eadc written by user to enable ??or disable ??adc interrupt. 5 et2 written by user to enable ??or disable ??timer 2 interrupt. 4e sw ritten by user to enable ??or disable ??uart serial port interrupt. 3 et1 written by user to enable ??or disable ??timer 1 interrupt. 2 ex1 written by user to enable ??or disable ??external interrupt 1. 1 et0 written by user to enable ??or disable ??timer 0 interrupt. 0 ex0 written by user to enable ??or disable ??external interrupt 0. interrupt priority ip register sfr address b8h power-on default value 00h bit addressable yes i s pc d a p2 t ps p1 t p1 x p0 t p0 x p table xxiii. ip sfr bit designations bit name description 7 psi written by user to select i 2 c/spi priority (??= high; ??= low). 6 padc written by user to select adc interrupt priority (??= high; ??= low). 5 pt2 written by user to select timer 2 interrupt priority (??= high; ??= low). 4p sw ritten by user to select uart serial port interrupt priority (??= high; ??= low). 3 pt1 written by user to select timer 1 interrupt priority (??= high; ??= low). 2 px1 written by user to select external interrupt 1 priority (??= high; ??= low). 1 pt0 written by user to select timer 0 interrupt priority (??= high; ??= low). 0 px0 written by user to select external interrupt 0 priority (??= high; ??= low).
rev. d ADUC812 ?9 secondary interrupt ie2 enable register sfr address a9h power-on default value 00h bit addressable no i m s p ei s e table xxiv. ie2 sfr bit designations bit name description 7 reserved for future use. 6 reserved for future use. 5 reserved for future use. 4 reserved for future use. 3 reserved for future use. 2 reserved for future use. 1 epsmi written by user to enable ??or disable ??power supply monitor interrupt. 0 esi written by user to enable ??or disable ??i 2 c/spi serial port interrupt. interrupt priority the interrupt enable registers are written by the user to enable individual interrupt sources, while the interrupt priority registers allow the user to select one of two priority levels for each interrupt. an interrupt of high priority may interrupt the service routine of a low priority interrupt. if two interrupts of different priorities occur at the same time, the higher level interrupt will be served first. an interrupt cannot be interrupted by another interrupt of the same priority level. if two interrupts of the same priority level occur simultaneously, a polling sequence is observed, as shown in table xxv. table xxv. priority within an interrupt level source priority description psmi 1 (highest) power supply monitor interrupt ie0 2 external interrupt 0 adci 3 adc interrupt tf0 4 timer/counter 0 interrupt ie1 5 external interrupt 1 tf1 6 timer/counter 1 interrupt i2ci + ispi 7 i 2 c/spi interrupt ri + ti 8 serial interrupt tf2 + exf2 9 (lowest) timer/counter 2 interrupt interrupt vectors when an interrupt occurs, the program counter is pushed onto the stack and the corresponding interrupt vector address is l oaded into the program counter. the interrupt vector addresses are shown in the table xxvi. table xxvi. interrupt vector addresses source vector address ie0 0003h tf0 000bh ie1 0013h tf1 001bh ri + ti 0023h tf2 + exf2 002bh adci 0033h i2ci + ispi 003bh psmi 0043h
rev. d ADUC812 ?0 ADUC812 hardware design considerations this section outlines some of the key hardware design consider- ations that must be addressed when integrating the ADUC812 into any hardware system. clock oscillator the clock source for the ADUC812 can come either from an external source or from the internal clock oscillator. to use the in ternal clock oscillator, connect a parallel resonant crystal between pins 32 and 33, and connect a capacitor from each pin to ground as shown below. xtal2 xtal1 to internal timing circuits ADUC812 figure 35. external parallel resonant crystal connections xtal2 xtal1 to internal timing circuits ADUC812 external clock source figure 36. connecting an external clock source whether using the internal oscillator or an external clock source, the ADUC812? specified operational clock speed range is 300 khz to 16 mhz. the core is static, and will function all the way down to dc. but at clock speeds slower that 400 khz the adc will no longer function correctly. therefore, to ensure specified o peration, use a clock frequency of at least 400 khz and no more than 16 mhz. external memory interface in addition to its internal program and data memories, the ADUC812 can access up to 64 k bytes of external program memory (rom, prom, etc.) and up to 16 m bytes of exter- nal data memory (sram). to select from which code space (internal or external program memory) to begin executing instructions, tie the ea (external access) pin high or low, respectively. when ea is high (pulled up to v dd ), user program execution will start at address 0 of the internal 8 k bytes flash/ee code space. when ea is low (tied to ground) u ser program execution will start at address 0 of the external code space. in either case, addresses above 1 fffh (8k) are mapped to the external space. note that a second very important function of the ea pin is described in the single pin emulation mode section. external program memory (if used) must be connected to the ADUC812 as illustrated in figure 37. note that 16 i/o lines (ports 0 and 2) are dedicated to bus functions during external program memory fetches. port 0 (p0) serves as a multiplexed address/data bus. it emits the low byte of the program counter (pcl) as an address, and then goes into a float state awaiting the arrival of the code byte from the program memory. during the time that the low byte of the program counter is valid on p0, the signal ale (address latch enable) clocks this byte into an address latch. meanwhile, port 2 (p2) emits the high byte of the program counter (pch), then psen strobes the eprom and the code byte is read into the ADUC812. latch eprom oe a8?15 a0?7 d0?7 (instruction) ADUC812 psen p2 ale p0 figure 37. external program memory interface note that program memory addresses are always 16 bits wide, even in cases where the actual amount of program memory used is less than 64 k bytes. external program execution sacrifices two of the 8-bit ports (p0 and p2) to the function of addressing the program memory. while executing from external program memory, ports 0 and 2 can be used simultaneously for read/write access to external data memory, but not for general-purpose i/o. though both external program memory and external data memory are accessed by some of the same pins, the two are completely independent of each other from a software point of view. for example, the chip can read/write external data memory while executing from external program memory. figure 38 shows a hardware configuration for accessing up to 64 k bytes of external ram. this interface is standard to any 8051 compatible mcu. latch sram oe a8?15 a0?7 d0?7 (data) ADUC812 rd p2 ale p0 we wr figure 38. external data memory interface (64k ad dress space)
rev. d ADUC812 ?1 if access to more than 64k bytes of ram is desired, a feature unique to the ADUC812 allows addressing up to 16 mbytes of external ram simply by adding an additional latch as illus- trated in figure 39. latch ADUC812 rd p2 ale p0 wr latch sram oe a8?15 a0?7 d0?7 (data) we a16?23 figure 39. external data memory interface (16 m bytes ad dress space) in either implementation, port 0 (p0) serves as a multiplexed address/data bus. it emits the low byte of the data pointer (dpl) as an address, which is latched by a pulse of ale prior to data being placed on the bus by the ADUC812 (write operation) or the sram (read operation). port 2 (p2) provides the data pointer page byte (dpp) to be latched by ale, followed by the data pointer high byte (dph). if no latch is connected to p2, dpp is ignored by the sram and the 8051 standard of 64k byte ex ternal data memory access is maintained. detailed timing diagrams of external program and data memory read and write access can be found in the timing specifica- tion sections. power-on reset operation e xternal por (power-on reset) circuitry must be implemented to drive the reset pin of the ADUC812. the circuit must hold the reset pin asserted (high) whenever the power supply (dv dd ) is below 2.5 v. furthermore, v dd must remain above 2.5 v for at least 10 ms before the reset signal is deasserted (low), by which time the power supply must have reached at least a 2.7 v level. the external por circuit must be operational down to 1.2 v or less. the timing diagram in figure 40 illus- trates this functionality under three separate events: power-up, brownout, and power-down. notice that when reset is asserted (high), it tracks the voltage on dv dd . these recommendations m ust be adhered to through the manufacturing flow of your ADUC812 based system as well as during its normal power-on o peration. failure to adhere to these recommendations can result in permanent damage to device functionality. 10ms min 1.2v max 10ms min 2.5v min 1.2v max dv dd reset figure 40. external por timing the best way to implement an external por function to meet the above requirements involves the use of a dedicated por chip, such as the adm809/adm810 sot-23 packaged pors from analog devices. recommended connection diagrams for both active high adm810 and active low adm809 pors are shown in figure 41 and figure 42, respectively. dv dd reset 48 34 20 15 ADUC812 por (active high) power supply figure 41. external active high por circuit some active-low por chips, such as the adm809, can be used with a manual push-button as an additional reset source as illustrated by the dashed line connection in figure 42. dv dd reset 48 34 20 ADUC812 15 optional manual reset p us h b u tt o n por (active low) power supply 1k figure 42. external active low por circuit power supplies the ADUC812? operational power supply voltage range is 2.7 v to 5.25 v. although the guaranteed data sheet specifications are given only for power supplies within 2.7 v to 3.6 v or 10% of the nominal 5 v level, the chip will function equally well at any power supply level between 2.7 v and 5.5 v. separate analog and digital power supply pins (av dd and dv dd, respectively) allow av dd to be kept relatively free of noisy digital signals often present on the system dv dd line. however, though you can power av dd and dv dd from two separate supplies if desired, you must ensure that they remain within 0.3 v of one another at all times in order to avoid damaging the chip (as per the absolute maximum ratings section). therefore it is recommended that unless av dd and dv dd are connected directly together, you connect back-to-back schottky diodes between them as shown in figure 43. dv dd 48 34 20 ADUC812 5 6 agnd av dd + 0.1 f 10 f analog supply 10 f dgnd 35 21 47 0.1 f + digital supply figure 43. external dual-supply connections
rev. d ADUC812 ?2 as an alternative to providing two separate power supplies, the user can help keep av dd quiet by placing a small series resistor and/or ferrite bead between it and dv dd , and then decoupling av dd separately to ground. an example of this configuration is shown in figure 44. with this configuration, other analog circuitry (such as op amps, voltage reference, and so on) can be powered from the av dd supply line as w ell. the user will still want to include back-to-back schottky diodes between av dd and dv dd in order to protect from power-up and power-down transient conditions that could separate the two supply voltages momentarily. dv dd 48 34 20 ADUC812 5 6 agnd av dd 0.1 f 10 f dgnd 35 21 47 0.1 f + digital supply 10 f 1.6 bead figure 44. external single-supply connections notice that in both figure 43 and figure 44, a large value (10 m f) reservoir capacitor sits on dv dd and a separate 10 m f capacitor sits on av dd . also, local small value (0.1 m f) capacitors are located at each v dd pin of the chip. as per standard design prac- tice, be sure to include all of these capacitors, and ensure the smaller capacitors are close to each av dd pin with trace lengths as short as possible. connect the ground terminal of each of these capacitors directly to the underlying ground plane. finally, it should also be noted that, at all times, the analog and digital ground pins on the ADUC812 must be referenced to the same system ground reference point. power consumption the currents consumed by the various sections of the ADUC812 are shown in table xxvii. the core values given represent the current drawn by dv dd , while the rest (adc, dac, volt- age reference) are pulled by the av dd pin and can be disabled in software when not in use. the other on-chip peripherals (watch dog timer, power supply monitor, and so on) consume negligible current and are therefore lumped in with the core operating current here. of course, the user must add any cur rents sourced by the dac or the parallel and serial i/o pins, in order to determine the total current needed at the ADUC812? supply pins. also, current drawn from the dv dd supply will increase by approximately 10 ma during flash/ee erase and program cycles. table xxvii. typical i dd of core and peripherals v dd = 5 v v dd = 3 v core (normal mode) (1.6 nas mclk) + (0.8 nas mclk) + 6 ma 3 ma core (idle mode) (0.75 nas mclk) + (0.25 nas mclk) + 5 ma 3 ma adc 1.3 ma 1.0 ma dac (each) 250 m a 200 m a voltage ref 200 m a 150 m a since operating dv dd current is primarily a function of clock speed, the expressions for core supply current in table xxvii are given as functions of mclk, the oscillator frequency. plug in a value for mclk in hertz to determine the current consumed by the core at that oscillator frequency. since the adc and dacs can be enabled or disabled in software, add only the currents from the peripherals you expect to use. the internal voltage refer- ence is automatically enabled whenever either the adc or at least one dac is enabled. and again, do not forget to include current sourced by i/o pins, serial port pins, dac outputs, and so forth, plus the additional current drawn during flash/ee erase and program cycles. a software switch allows the chip to be switched from normal mode into idle mode, and also into full power-down mode. below are brief descriptions of power-down and idle modes. in idle mode, the oscillator continues to run but is gated off to the core only. the on-chip peripherals continue to receive the clock, and remain functional. port pins and dac output pins retain their states in this mode. the chip will recover from idle mode upon receiving any enabled interrupt, or upon receiving a hardware reset. in full power-down mode, the on-chip oscillator stops, and all on-chip peripherals are shut down. port pins retain their logic levels in this mode, but the dac output goes to a high impedance state (three-state). the chip will only recover from power-down mode upon receiving a hardware reset or when power is cycled. during full power-down mode, the ADUC812 consumes a total of approximately 5 m a.
rev. d ADUC812 ?3 grounding and board layout recommendations as with all high resolution data converters, special attention must be paid to gr ounding and pc board layout of ADUC812 based designs in order to achieve optimum performance from th e adc and dacs. although the ADUC812 has separate pins for analog and digital ground (agnd and dgnd), the user must not tie these to two separate ground planes unless the two ground planes are connected together very close to the ADUC812, as illustrated in the simpli- fied example of figure 45a. in systems where digital and analog ground planes are connected together somewhere else (for example, at the system? power supply), they cannot be connected again near the ADUC812 since a ground loop would result. in these cases, tie the ADUC812? agnd and dgnd pins all to the analog ground plane, as illustrated in figure 45b. in systems with only one ground plane, ensure that the digital and analog com- ponents are physically separated onto separate halves of the board such that digital return currents do not flow near analog circuitry and vice versa. the ADUC812 can then be placed between the digital and analog sections, as illustrated in figure 45c. in all of these scenarios, and in more complicated real-life appli- cations, keep in mind the flow of current from the supplies and back to ground. make sure the return paths for all currents are as close as possible to the paths the currents took to reach their destinations. for example, do not power components on the analog side of figure 45b with dv dd since that would force return currents from dv dd to flow through agnd. also, try to avoid digital currents flowing under analog circuitry, which could happen if the user placed a noisy digital chip on the left half of the board in figure 45c. whenever possible, avoid large discontinuities in the ground plane(s) (formed by a long trace on the same layer), since they force return signals to travel a longer path. and of course, make all connections to the ground plane directly, with little or no trace separating the pin from its via to ground. if the user plans to connect fast logic signals (rise/fall time < 5 ns) to any of the ADUC812? digital inputs, add a series resistor to each relevant line to keep rise and fall times longer than 5 ns at the ADUC812 input pins. a value of 100 w or 200 w is usually suffi- cient to prevent high speed signals from coupling capacitively into the ADUC812 and affecting the accuracy of adc conversions. b. dgnd agnd place analog components here place digital components here c. gnd place analog components here place digital components here dgnd agnd place analog components here a. place digital components here figure 45. system grounding schemes
rev. d ADUC812 ?4 c1+ v+ c1 c2+ c2 v t2out r2in v cc gnd t1out r1in r1out t1in t2in r2out adm202 dv dd 27 34 33 31 30 29 28 39 38 37 36 35 32 40 47 46 44 43 42 41 52 51 50 49 48 45 dv dd 1k dv dd 1k 2-pin header for emulation access (normally open) download/debug enable jumper (normally open) 11.0592mhz dv dd 1 9-pin d-sub female 2 3 4 5 6 7 8 9 av dd av dd agnd c ref v ref dac0 dac1 dv dd dgnd psen ea dgnd dv dd xtal2 xtal1 reset rxd txd dv dd dgnd adm810 v cc rst gnd not connected in this example dv dd ADUC812 dac output 51 v ref output adc0 adc7 analog input dv dd figure 46. typical system configuration other hardware considerations to facilitate in-circuit programming, plus in-circuit debug and emulation options, users w ill want to implement some simple co nn ection points in their hardware that will allow easy access to download, debug, and emulation modes. in-circuit serial download access nearly all ADUC812 designs will want to take advantage of the in-circuit reprogrammability of the chip. this is accomplished by a connection to the ADUC812? uart, which requires an external rs-232 chip for level translation if downloading code from a pc. basic configuration of an rs-232 connection is illustrated in figure 46 with a simple adm202 based circuit. if users would rather not design an rs-232 chip onto a board, refer to the appli- cation note, uc006? 4-wire uart-to-pc interface, (available at www.analog.com/microconverter) for a simple (and zero-cost- per-board) method of gaining in-circuit serial download access to the ADUC812. in addition to the basic uart connections, users will also need a way to trigger the chip into download mode. this is accom- plished via a 1 k w pull-down resistor that can be jumpered onto the psen pin, as shown in figure 46. to get the ADUC812 into download mode, simply connect this jumper and power- cycle the device (or manually reset the device, if a manual reset button is available) and it will be ready to receive a new program serially. with the jumper removed, the device will come up in normal mode (and run the program) whenever power is cycled or reset is toggled. note that psen is normally an output (as described in the external memory interface section), and is sampled as an input only on the falling edge of reset (i.e., at power-up or upon an external manual reset). note also that if any external circuitry uninten- tionally pulls psen low during power-up or reset events, it could cause the chip to enter download mode and therefore fail to begin user code execution as it should. to prevent this, ensure that no external signals are capable of pulling the psen pin low, except for the external psen jumper itself. embedded serial port debugger from a hardware perspective, entry to serial port debug mode is identical to the serial download entry sequence described above. in fact, both serial download and serial port debug modes can be th ought of as essentially one mode of operation used in two different ways.
rev. d ADUC812 ?5 n ote that the serial port debugger is fully contained on the ADUC812 device, (unlike rom monitor type debuggers) and therefore no external memory is needed to enable in-system debug sessions. single-pin emulation mode also built into the ADUC812 is a dedicated controller for single-pin in-circuit emulation (ice) using standard production ADUC812 devices. in this mode, emulation access is gained by connection to a single pin, the ea pin. normally, this pin is hardwired either high or low to select execution from internal or external program memory space, as described earlier. to enable single-pin emulation mode, however, users will need to pull the ea pin high through a 1 k w resistor, as shown in figure 46. the emulator will then connect to the 2-pin header also shown in figure 46. to be com- patible with the standard connector that comes with the single-pin emulator available from accutron limited (www.accutron.com), use a 2-pin 0.1 inch pitch ?riction lock?header from molex (www.molex.com) such as their part number 22-27-2021. be sure to observe the polarity of this header. as represented in figure 46, when the friction lock tab is at the right, the ground pin should be the lower of the two pins (when viewed from the top). enhanced-hooks emulation mode ADUC812 also supports enhanced-hooks emulation mode. an enhanced-hooks based emulator is available from metalink corporation (www.metaice.com). no special hardware support for these emulators needs to be designed onto the board since these are pod-style emulators where users must replace the chip on their board with a header device that the emulator pod plugs into. the only hardware concern is then one of determining if adequate space is available for the emulator pod to fit into the system enclosure. typical system configuration a typical ADUC812 configuration is shown in figure 46. it sum- marizes some of the hardware considerations discussed in the previous paragraphs. quickstart development system the quickstart development system is a full featured, low cost development tool suite supporting the ADUC812. the system consists of the following pc based (windows compatible) h ard ware and software development tools. hardware: ADUC812 evaluation board, plug-in power supply and serial port c able code development: 8051 assembler code functionality: windows based simulator in-circuit code download: serial downloader in-circuit debugger: serial port debugger miscellaneous other: cd-rom documentation and two additional prototype devices figure 47 shows the typical components of a quickstart devel opment system. a brief description of some of the software tools components in the quickstart development system is given in the following sections. figure 47. components of the quickstart development system figure 48. typical debug session download?n-circuit serial downloader the serial downloader is a windows application that allows the user to serially download an assembled program (intel hex format file) to the on-chip program flash memory via the serial com1 port on a standard pc. application note uc004 detailing this serial download protocol is available at www.analog.com/ microconverter. debug?n-circuit debugger the debugger is a windows application that allows the user to debug code execution on silicon using the microconverter uart serial port. the debugger provides access to all on-chip periph- erals during a typical debug session as well as single-step and breakpoint code execution control. adsim?indows simulator the simulator is a windows application that fully simulates all the microconverter functionality including adc and dac peripherals. the simulator provides an easy-to-use, intuitive in ter- face to the microconverter functionality and integrates many standard debug features including multiple breakpoints, single stepping, and code execution trace capability. this tool can be used both as a tutorial guide to the part as well as an efficient way to prove code functionality before moving to a hardware plat form. the quickstart development tool suite software is freely available at the analog devices microconverter website, www.analog.com/ microconverter.
rev. d ADUC812 ?6 12 mhz variable clock parameter min typ max min typ max unit clock input (external clock driven xtal1) t ck xtal1 period 83.33 62.5 1000 ns t ckl xtal1 width low 20 20 ns t ckh xtal1 width high 20 20 ns t ckr xtal1 rise time 20 20 ns t ckf xtal1 fall time 20 20 ns t cyc 4 ADUC812 machine cycle time 1 12t ck m s notes 1 ac inputs during testing are driven at dv dd 0.5 v for a logic 1 and 0.45 v for a logic 0. timing measurements are made at v ih min for a logic 1 and v il max for a logic 0. 2 for timing purposes, a port pin is no longer floating when a 100 mv change from load voltage occurs. a port pin begins to float when a 100 mv change from the loaded v oh /v ol level occurs. 3 c load for port 0, ale, psen outputs = 100 pf; c load for all other outputs = 80 pf, unless otherwise noted. 4 ADUC812 machine cycle time is nominally defined as mclkin/12. t ckl t ckf t ck t ckh t ckr figure 49. xtal 1 input dv dd ?0.5v 0.45v 0.2v cc + 0.9v test points 0.2v cc ?0.1v v load ?0.1v v load v load + 0.1v timing reference points v load ?0.1v v load v load ?0.1v figure 50. timing waveform characteristics (av dd = dv dd = 3.0 v or 5.0 v 10%. all specifications t a = t min to t max , unless otherwise noted.) timing specifications 1, 2, 3
rev. d ?7 ADUC812 12 mhz variable clock parameter min max min max unit external program memory read cycle t lhll ale pulsewidth 127 2t ck ?0 ns t avll address valid to ale low 43 t ck ?0 ns t llax address hold after ale low 53 t ck ?0 ns t lliv ale low to valid instruction in 234 4t ck 100 ns t llpl ale low to psen low 53 t ck ?0 ns t plph psen pulsewidth 205 3t ck ?5 ns t pliv psen low to valid instruction in 145 3t ck 105 ns t pxix input instruction hold after psen 00 ns t pxiz input instruction float after psen 59 t ck ?5 ns t aviv address to valid instruction in 312 5t ck 105 ns t plaz psen low to address float 25 25 ns t phax address hold after psen h igh 0 0 ns mclk ale (o) psen (o) port 0 (i/o) port 2 (o) t lhll t avll t llpl t plph t lliv t pliv t plaz t llax t pxix t pxiz t phax t aviv pcl (out) instruction (in) pch figure 51. external program memory read cycle
rev. d ADUC812 ?8 12 mhz variable clock parameter min max min max unit external data memory read cycle t rlrh rd pulsewidth 400 6t ck 100 ns t avll address valid after ale low 43 t ck ?0 ns t llax address hold after ale low 48 t ck ?5 ns t rldv rd low to valid data in 252 5t ck 165 ns t rhdx data and address hold after rd 00 ns t rhdz data float after rd 97 2t ck ?70 ns t lldv ale low to valid data in 517 8t ck 150 ns t avdv address to valid data in 585 9t ck 165 ns t llwl ale low to rd or wr low 200 300 3t ck ?0 3t ck +50 ns t avwl address valid to rd or wr low 203 4t ck 130 ns t rlaz rd low to address float 0 0 ns t whlh rd or wr high to ale high 43 123 t ck ?0 6t ck 100 ns mclk ale (o) psen (o) rd (o) port 0 (i/o) port 2 (o) t whlh t lldv t llwl t rlrh t avwl t llax t avll t rlaz t rhdx t rhdz t avdv a0?7 (out) data (in) a16?23 a8?15 t rldv figure 52. external data memory read cycle
rev. d ?9 ADUC812 12 mhz variable clock parameter min max min max unit external data memory write cycle t wlwh wr pulsewidth 400 6t ck 100 ns t avll address valid after ale low 43 t ck ?0 ns t llax address hold after ale low 48 t ck ?5 ns t llwl ale low to rd or wr low 200 300 3t ck ?0 3t ck +50 ns t avwl address valid to rd or wr low 203 4t ck 130 ns t qvwx data valid to wr transition 33 t ck ?0 ns t qvwh data setup before wr 433 7t ck 150 ns t whqx data and address hold after wr 33 t ck ?0 ns t whlh rd or wr high to ale high 43 123 t ck ?0 6t ck 100 ns mclk ale (o) psen (o) wr (o) port 2 (o) t whlh t wlwh t llwl t avwl t llax t avll t qvwx t qvwh t whqx a0?7 data a16?23 a8?15 figure 53. external data memory write cycle
rev. d ADUC812 ?0 12 mhz variable clock parameter min typ max min typ max unit uart timing (shift register mode) t xlxl serial port clock cycle time 1.0 12t ck m s t qvxh output data setup to clock 700 10t ck ?133 ns t dvxh input data setup to clock 300 2t ck + 133 ns t xhdx input data hold after clock 0 0 ns t xhqx output data hold after clock 50 2t ck ?117 ns ale (o) txd (output clock) rxd (output data) rxd (input data) t xlxl t qvxh t xhqx t dvxh t xhdx set ri or set ti 0 6 msb bit6 bit1 msb bit6 bit1 lsb 7 lsb 1 figure 54. uart timing in shift register mode
rev. d ?1 ADUC812 parameter min max unit i 2 c compatible interface timing t low sclock low pulsewidth 1.3 m s t high sclock high pulsewidth 0.6 m s t hd; sta start condition hold time 0.6 m s t su; dat data setup time 100 m s t hd; dat data hold time 0 0.9 m s t su; sta setup time for repeated start 0.6 m s t su; sto stop condition setup time 0.6 m s t buf bus free time between a stop condition and a start condition 1.3 m s t r rise time for both sclock and sdata 300 ns t f fall time for both sclock and sdata 300 ns t sup 1 pulsewidth of spike suppressed 50 ns sdata (i/o) sclk (i) stop condition start condition ps repeated start s(r) 1 2? 8 1 msb t buf t sup t sup t r t r t f lsb ack msb t su ; sto t hd; sta t hd; sta t hd; dat t low t high t su; dat t su; sta 9 t hd; dat figure 55. i 2 c compatible interface timing
rev. d ADUC812 ?2 parameter min typ max unit spi master mode timing (cpha = 1) t low sclock low pulsewidth 330 ns t sh sclock high pulsewidth 330 ns t dav data output valid after sclock edge 50 ns t dsu data input setup time before sclock edge 100 ns t dhd data input hold time after sclock edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns mosi sclock (cpol = 1) sclock (cpol = 0) t sh t sl t sr t sf bit 6? lsb in t dr miso t dav t df t dsu msb bit 6? lsb t dhd msb in figure 56. spi master mode timing (cpha = 1)
rev. d ?3 ADUC812 parameter min typ max unit spi master mode timing (cpha = 0) t sl sclock low pulsewidth 330 ns t sh sclock high pulsewidth 330 ns t dav data output valid after sclock edge 50 ns t dosu data output setup before sclock edge 150 ns t dsu data input setup time before sclock edge 100 ns t dhd data input hold time after sclock edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns t dav miso mosi sclock (cpol = 1) sclock (cpol = 0) t sh t sl t sr t sf t dosu t df t dr t dsu t dhd msb bit 6? lsb bit 6? lsb in msb in figure 57. spi master mode timing (cpha = 0)
rev. d ADUC812 ?4 parameter min typ max unit spi slave mode timing (cpha = 1) t ss ss to sclock edge 0 ns t sl sclock low pulsewidth 330 ns t sh sclock high pulsewidth 330 ns t dav data output valid after sclock edge 50 ns t dsu data input setup time before sclock edge 100 ns t dhd data input hold time after sclock edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns t sfs ss high after sclock edge 0 ns miso mosi sclock (cpol = 1) sclock (cpol = 0) t sh t sr t sf t dav t dr msb lsb t sfs t ss ss bit 6? bit 6? t sl lsb in msb in t dsu t dhd t df figure 58. spi slave mode timing (cpha = 1)
rev. d ?5 ADUC812 parameter min typ max unit spi slave mode timing (cpha = 0) t ss ss to sclock edge 0 ns t sl sclock low pulsewidth 330 ns t sh sclock high pulsewidth 330 ns t dav data output valid after sclock edge 50 ns t dsu data input setup time before sclock edge 100 ns t dhd data input hold time after sclock edge 100 ns t df data output fall time 10 25 ns t dr data output rise time 10 25 ns t sr sclock rise time 10 25 ns t sf sclock fall time 10 25 ns t doss data output valid after ss e dge 20 ns t sfs ss high after sclock edge 0 ns t dav t sfs miso mosi sclock (cpol = 1) sclock (cpol = 0) t sh t sl t sr t df t dr t dsu t dhd t ss ss t doss msb bit 6? lsb bit 6? lsb in msb in t sf figure 59. spi slave mode timing (cpha = 0)
rev. d ADUC812 ?6 outline dimensions 52-lead plastic quad flatpack [mqfp] (s-52) dimensions shown in millimeters seating plane view a 0.23 0.11 2.45 max 1.03 0.88 0.73 top view (pins down) 1 39 40 13 14 27 26 52 pin 1 0.65 bsc 13.45 13.20 sq 12.95 7.80 ref 10.20 10.00 sq 9.80 0.40 0.22 view a rotated 90 ccw 7 0 2.20 2.00 1.80 0.10 min coplanarity compliant to jedec standards mo-022-ac 56-lead frame chip scale package [lfcsp] 8 x 8 mm body (cp-56) dimensions shown in millimeters pin 1 indicator top view 7.75 bsc sq 8.00 bsc sq 1 56 14 15 43 42 28 29 bottom view 6.25 6.10 5.95 0.50 0.40 0.30 0.30 0.23 0.18 0.50 bsc 12 max 0.20 ref 1.00 max 0.65 nom 1.00 0.90 0.80 6.50 ref seating plane 0.10 max 0.60 max 0.60 max pin 1 indicator compliant to jedec standards mo-220-vlld-2 coplanarity 0.08 sq
rev. d ADUC812 ?7 revision history location page 2/03?ata sheet changed from rev. c to rev. d. added cp-56 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . global edits to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 added 56-lead lfcsp pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 updated ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 added i2c compatible interface timing table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 added new figure 55 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 updated outline dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 03/02?ata sheet changed from rev. b to rev. c. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edits to pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to pin function descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 edits to figure 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 edits to serial peripheral interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 edits to table xi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 edits to table xxiii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 edits to tables xxiv, xxv, and xxvi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 10/01?ata sheet changed from rev. a to rev. b. entire data sheet revised . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . all
?8
?9
?0 c00208??/03(d) printed in u.s.a.

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